Modeling Dynamic Interplay Between Charge Traps and Polarization for Memory Window Enhancement in Gate Injection Layers.

Enhanced Memory Performance in Ferroelectric NAND Applications: The Role of Tunnel Dielectric Position for Robust 10-Year Retention.

Retention Analysis of Ferroelectric FETs with Gate-Side Injection for Vertical NAND Storage.

Investigating Read-After-Write Delay in Ferroelectric FET with Gate-Side Injection.

The Opportunity of Anti-ferroelectrics in FeFET for Emerging Non-Volatile Memory Applications.

Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch.

Highly Robust All-Oxide Transistors with Ultrathin In2O3 as Channel and Thick In2O3 as Metal Gate Towards Vertical Logic and Memory.

Ge(110) GAA Nanosheet / Si(100) Tri-gate Nanosheet Monolithic CFETs Featuring Record-High Hole Mobility.

In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling.

Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-k of 70 for DRAM Technology.

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND.

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET.

Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node.

Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation.

Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND.

Prospective Innovation of DRAM, Flash, and Logic Technologies for Digital Transformation (DX) Era.

12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis.