2016
Array Size Computation under Uniform Overlapping and Irregular Accesses.
ACM Trans. Design Autom. Electr. Syst., 2016
Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures.
Microprocess. Microsystems, 2016
Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs.
J. Circuits Syst. Comput., 2016
2015
A methodology for speeding up matrix vector multiplication for single/multi-core architectures.
J. Supercomput., 2015
A methodology for speeding up loop kernels by exploiting the software information and the memory architecture.
Comput. Lang. Syst. Struct., 2015
Hardware implementation of the Totally Self-Checking SHA-256 hash core.
Proceedings of the IEEE EUROCON 2015, 2015
2014
A Methodology for Speeding up MVM for Regular, Toeplitz and Bisymmetric Toeplitz Matrices.
J. Signal Process. Syst., 2014
A Matrix-Matrix Multiplication methodology for single/multi-core architectures using SIMD.
J. Supercomput., 2014
A methodology for speeding up edge and line detection algorithms focusing on memory architecture utilization.
J. Supercomput., 2014
A scalable and near-optimal representation of access schemes for memory management.
ACM Trans. Archit. Code Optim., 2014
On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs.
Integr., 2014
Optimising the SHA-512 cryptographic hash function on FPGAs.
IET Comput. Digit. Tech., 2014
2013
Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes.
ACM Trans. Design Autom. Electr. Syst., 2013
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints.
ACM Trans. Archit. Code Optim., 2013
A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families.
J. Circuits Syst. Comput., 2013
High-performance FPGA implementations of the cryptographic hash function JH.
IET Comput. Digit. Tech., 2013
A systematic approach to classify design-time global scheduling techniques.
ACM Comput. Surv., 2013
2012
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC.
ACM Trans. Reconfigurable Technol. Syst., 2012
A data locality methodology for matrix-matrix multiplication algorithm.
J. Supercomput., 2012
On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function.
Proceedings of the SECRYPT 2012, 2012
High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach.
Proceedings of the SECRYPT 2012, 2012
A template-based methodology for efficient microprocessor and FPGA accelerator co-design.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
2011
A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization.
IEEE Trans. Signal Process., 2011
Cipher Block Based Authentication Module: a Hardware Design Perspective.
J. Circuits Syst. Comput., 2011
2010
Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy.
J. Signal Process. Syst., 2010
Ultra High Speed SHA-256 Hashing Cryptographic Module for IPSec Hardware/Software Codesign.
Proceedings of the SECRYPT 2010, 2010
Exploration of cryptographic ASIP designs for wireless sensor nodes.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays.
J. Supercomput., 2009
A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores.
IEEE Trans. Dependable Secur. Comput., 2009
Resource aware mapping on coarse grained reconfigurable arrays.
Microprocess. Microsystems, 2009
Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse.
IET Comput. Digit. Tech., 2009
2008
Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path.
J. Signal Process. Syst., 2008
Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path.
J. Syst. Archit., 2008
Efficient high-performance implementation of JPEG-LS encoder.
J. Real Time Image Process., 2008
Novel Hardware Implementation of the Cipher Message Authentication Code.
J. Comput. Networks Commun., 2008
Integrating high speed multipliers in Coarse Grain Reconfigurable Arrays.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
2007
Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Speedups in embedded systems with a high-performance coprocessor datapath.
ACM Trans. Design Autom. Electr. Syst., 2007
Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path.
J. Supercomput., 2007
Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture.
J. Supercomput., 2007
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms.
Microprocess. Microsystems, 2007
Server side hashing core exceeding 3 Gbps of throughput.
Int. J. Secur. Networks, 2007
Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Throughput Optimization of the Cipher Message Authentication Code.
Proceedings of the 15th International Conference on Digital Signal Processing, 2007
Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Compiler assisted architectural exploration for coarse grained reconfigurable arrays.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Implementation of HSSec: a high-speed cryptographic co-processor.
Proceedings of 12th IEEE International Conference on Emerging Technologies and Factory Automation, 2007
Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
A unified evaluation framework for coarse grained reconfigurable array architectures.
Proceedings of the 4th Conference on Computing Frontiers, 2007
2006
High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications.
J. Supercomput., 2006
Partitioning Methodology for Heterogeneous Reconfigurable Functional Units.
J. Supercomput., 2006
Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs.
J. Supercomput., 2006
A high-performance data path for synthesizing DSP kernels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems.
Microelectron. J., 2006
Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006
Mapping DSP applications on processor/coarse-grain reconfigurable array architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Resource constrained modulo scheduling for coarse-grained reconfigurable arrays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels.
J. Circuits Syst. Comput., 2005
A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000.
Integr., 2005
Comparison of the Hardware Implementation of Stream Ciphers.
Int. Arab J. Inf. Technol., 2005
A method for partitioning applications in hybrid reconfigurable architectures.
Des. Autom. Embed. Syst., 2005
Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study.
Proceedings of the Integrated Circuit and System Design, 2005
Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs.
Proceedings of the Integrated Circuit and System Design, 2005
A low-power and high-throughput implementation of the SHA-1 hash function.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A methodology for partitioning DSP applications in hybrid reconfigurable systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Novel high throughput implementation of SHA-256 hash function through pre-computation technique.
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Partitioning DSP applications to different granularity reconfigurable hardware.
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors.
J. VLSI Signal Process., 2004
A Framework for Data Partitioning for C++ Data-Intensive Applications.
Des. Autom. Embed. Syst., 2004
An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004
A Novel Data-Path for Accelerating DSP Kernels.
Proceedings of the Computer Systems: Architectures, 2004
A Novel Constant-Time Fault-Secure Binary Counter.
Proceedings of the Integrated Circuit and System Design, 2004
The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems.
Proceedings of the Integrated Circuit and System Design, 2004
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.
Proceedings of the Integrated Circuit and System Design, 2004
Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
A high performance data-path to accelerate DSP kernels.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Comparison of the hardware architectures and FPGA implementations of stream ciphers.
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path.
Proceedings of the Field Programmable Logic and Application, 2004
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms.
Proceedings of the 2004 Design, 2004
2003
Power efficient data path synthesis of sum-of-products computations.
IEEE Trans. Very Large Scale Integr. Syst., 2003
A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits.
J. Circuits Syst. Comput., 2003
Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications.
Des. Autom. Embed. Syst., 2003
A novel high-speed counter with counting rate independent of the counter's length.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Power aware data type refinement on the HIPERLAN/2.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores.
VLSI Design, 2002
Power Efficient Hierarchical Scheduling for DSP Transformations.
VLSI Design, 2002
A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Memory accesses reordering for interconnect power reduction in sum-of-products computations.
IEEE Trans. Signal Process., 2002
A fast and accurate delay dependent method for switching estimation of large combinational circuits.
J. Syst. Archit., 2002
Power Efficient Vector Quantization Design Using Pixel Truncation.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Confronting violations of the TSCG(T) in low-power design.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
A low power fault secure timer implementation based on the Gray encoding scheme.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
An efficient VLSI implementation for forward and inverse wavelet transform for JPEG2000.
Proceedings of the 14th International Conference on Digital Signal Processing, 2002
A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications.
Proceedings of the 2002 Design, 2002
2001
A Fast and Accurate Method of Power Estimation for Logic Level Networks.
VLSI Design, 2001
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model.
VLSI Design, 2001
Evaluation of design alternatives for the 2-D-discrete wavelet transform.
IEEE Trans. Circuits Syst. Video Technol., 2001
Performance comparison of DWT scheduling alternatives on programmable platforms.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Power, performance and area exploration of block matching algorithms mapped on programmable processors.
Proceedings of the 2001 International Conference on Image Processing, 2001
A local wavelet transform implementation versus an optimal row-column algorithm for the 2D multilevel decomposition.
Proceedings of the 2001 International Conference on Image Processing, 2001
Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
A code transformation-based methodology for improving I-cache performance.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Design of low-power on-line reconfigurable datapaths using self-checking circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Quantization effect on VLSI implementations for the 9/7 DWT filters.
Proceedings of the IEEE International Conference on Acoustics, 2001
A wavelet-tree image coding system with efficient memory utilization.
Proceedings of the IEEE International Conference on Acoustics, 2001
2000
A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints.
J. VLSI Signal Process., 2000
Low power architectures for digital signal processing.
J. Syst. Archit., 2000
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers.
Proceedings of the Integrated Circuit Design, 2000
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions.
Proceedings of the Integrated Circuit Design, 2000
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.
Proceedings of the Integrated Circuit Design, 2000
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance.
Proceedings of the Integrated Circuit Design, 2000
Low power synthesis of sum-of-products computation (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
A methodology for the behavioral-level event-driven power management of digital receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Low power design of a multi-mode transceiver.
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Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays.
J. VLSI Signal Process., 1999
A New Method for Low Power Design of Two-Level Logic Circuits.
VLSI Design, 1999
Computation Reordering: A Novel Transformation for Low Power DSP Synthesis.
VLSI Design, 1999
Novel techniques for bus power consumption reduction in realizations of sum-of-product computation.
IEEE Trans. Very Large Scale Integr. Syst., 1999
Strategy for power-efficient design of parallel systems.
IEEE Trans. Very Large Scale Integr. Syst., 1999
A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Power exploration of multimedia applications realized on embedded cores.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
An efficient probabilistic method for logic circuits using real delay gate model.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
The VLSI implementation of a baseband receiver for DECT-based portable applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Low power synthesis of sum-of-product computation in DSP algorithms.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
System-level power optimizing data-flow transformations for multimedia applications realized on programmable multimedia processors.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Fault secure binary counter design.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Hardware and Power Requirements of Self-checking circuits.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
Trade-Off Analysis of a Low-Power Image Coding Algorithm.
J. VLSI Signal Process., 1998
A novel algorithm for low-power image and video coding.
IEEE Trans. Circuits Syst. Video Technol., 1998
Novel codebook generation algorithms for vector quantization image compression.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Low-power implementation of discrete wavelet transform.
Proceedings of the 9th European Signal Processing Conference, 1998
Switching Response Modeling of the CMOS Inverter for Sub-micron Devices.
Proceedings of the 1998 Design, 1998
1996
Transformation of Nested Loops into Uniform Recurrences and their Mapping to Regular Processor Arrays.
J. Circuits Syst. Comput., 1996
A novel approach for reducing the switching activity in two-level logic circuits.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Low-power image decoding using fractals.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Accurate timing model for the CMOS inverter.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
1995
A floating-point advanced cordic processor.
J. VLSI Signal Process., 1995
Prime-factor DCT algorithms.
IEEE Trans. Signal Process., 1995
On the computation of the prime factor DST.
Signal Process., 1995
An ANNs-based system for the diagnosis and treatment of diseases.
Neural Process. Lett., 1995
Alternative Architectures for the 2-D DCT Algorithm.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Artificial neural networks in medical decision making systems: an application to pulmonary diseases' diagnosis through VHDL synthesis.
Proceedings of the 1995 European Design and Test Conference, 1995
1994
Array processor for block adaptive LS FIR filtering.
Signal Process., 1994
A bit-serial VLSI architecture for the 2-D discrete cosine transform.
Microprocess. Microprogramming, 1994
Experiences accumulated working towards medical decision support systems.
Microprocess. Microprogramming, 1994
Image coding using vector quantization of wavelet coefficients.
Microprocess. Microprogramming, 1994
A Fast DCT Processor, Based on Special Purpose CORDIC Rotators.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Near-Lossless Compression of Continuous-Tone Still Images Using Fuzzy Logic Notions and the Binary Arithmetic Coder (Q-Coder).
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
A CAD Tool for the Development of an Extra-Fast Fuzzy Logic Controller Based on FPGAs and Memory Modules.
Proceedings of the Field-Programmable Logic, 1994
1993
Real time Cepstrum computation based on an Advanced CORDIC processor.
Microprocess. Microprogramming, 1993
Implementation of Given's Rotation processors for DSP real-time applications.
Microprocess. Microprogramming, 1993
Development of a technology independent library.
Microprocess. Microprogramming, 1993
A Systematic Methodology for Designing Multilevel Systolic Architectures.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
CORDIC Based Pipeline Architecture for All-pass Filters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Space-Time Representation of Iterative Algorithms and The Design of Regular Processor Arrays.
Proceedings of the 1993 International Conference on Parallel Processing, 1993
Systematic design of full adder-based architectures for convolution.
Proceedings of the IEEE International Conference on Acoustics, 1993
1992
A VLSI synthesis tool for complementary output delta modulation FIR filters.
Microprocess. Microprogramming, 1992
An Efficient Decompostion Technique for Mapping Nested Loops with Constant Dependencies into Regular Processor Arrays.
J. Parallel Distributed Comput., 1992
A Systematic Partitioning Method for Designing Fixed-Size Processor Arrays.
J. Circuits Syst. Comput., 1992
Image reconstruction on a special purpose array processor.
Image Vis. Comput., 1992
A processor for time-varying digital audio filters with special transition properties.
Proceedings of the Fourth Euromicro workshop on Real-Time Systems, 1992
1991
Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations.
Microprocessing and Microprogramming, 1991
Array processor for LS FIR system identification.
Microprocessing and Microprogramming, 1991
A placing and routing tool implemented in Prolog.
Microprocessing and Microprogramming, 1991
Direct mapping of nested loops on piecewise regular processor arrays.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991
1990
A DSP processor with a powerful set of elementary arithmetic operations based on cordic and CCM algorithms.
Microprocessing and Microprogramming, 1990
A generator for a number format conversion IC.
Microprocessing and Microprogramming, 1990
1986
An optimal technique for constraint-based image restoration and reconstruction.
IEEE Trans. Acoust. Speech Signal Process., 1986
1985
Optimal techniques for constraint based signal restoration and image reconstruction.
Proceedings of the IEEE International Conference on Acoustics, 1985
Detection algorithms based on prediction error - additive noise - data orthogonality.
Proceedings of the IEEE International Conference on Acoustics, 1985
2-D Array processor having a controlled pipelined architecture for elliptical sparse matrices.
Proceedings of the IEEE International Conference on Acoustics, 1985
1984
Tomographic and spectral analysis using noise statistics.
Proceedings of the IEEE International Conference on Acoustics, 1984
Spectra using data distribution and covariance modelling.
Proceedings of the IEEE International Conference on Acoustics, 1984
1983
Reconstruction algorithms for limited view projection data.
Proceedings of the IEEE International Conference on Acoustics, 1983
1982
An optimal technique for tomographic image reconstruction from curved ray projections.
Proceedings of the IEEE International Conference on Acoustics, 1982
1978
Constraint optimization algorithms for digital image reconstruction from projections.
PhD thesis, 1978