A High-Speed 8-bit Single-Channel SAR ADC with Tailored Bit Intervals.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024
Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer.
IEEE Trans. Very Large Scale Integr. Syst., May, 2023
Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs.
IEEE Trans. Circuits Syst. II Express Briefs, 2019