First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s).
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Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
First Demonstration of High-Sensitivity (NEP 1fW<sup>1/2</sup>) Back-Illuminated Active-Matrix Deep UV Image Sensor by Monolithic Integration of Ga2O3 Photodetectors and Oxide Thin-Film-Transistors.
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Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Vertical Channel-All-Around (CAA) IGZO FET under 50 nm CD with High Read Current of 32.8 μA/μm (Vth + 1 V), Well-performed Thermal Stability up to 120 ℃ for Low Latency, High-density 2T0C 3D DRAM Application.
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Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Scaling Dual-Gate Ultra-thin a-IGZO FET to 30 nm Channel Length with Record-high Gm, max of 559 µS/µm at VDS=1 V, Record-low DIBL of 10 mV/V and Nearly Ideal SS of 63 mV/dec.
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Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A physical model for dual gate a-InGaZnO thin film transistors based on multiple trapping and release mechanism.
Microelectron. J., 2019
Flexible cation-based threshold selector for resistive switching memory integration.
Sci. China Inf. Sci., 2018