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2017
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.
[DOI]
Tah-Kang Joseph Ting
,
Gyh-Bin Wang
,
Ming-Hung Wang
,
Chun-Peng Wu
,
Chun-Kai Wang
,
Chun-Wei Lo
,
Li-Chin Tien
,
Der-Min Yuan
,
Yung-Ching Hsieh
,
Jenn-Shiang Lai
,
Wen-Pin Hsu
,
Chien-Chih Huang
,
Chi-Kang Chen
,
Yung-Fa Chou
,
Ding-Ming Kwai
,
Zhe Wang
,
Wei Wu
,
Shigeki Tomishima
,
Patrick Stolt
,
Shih-Lien Lu
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017