Hardware-Efficient Interpolation-Based QR Decomposition and Lattice Reduction Processor for MIMO-OFDM Receivers.
J. Signal Process. Syst., 2017
A 6.4G LLR/s 8×8 64-QAM soft-output MIMO detector with lattice reduction preprocessing.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
A 3.1 Gb/s 8 × 8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A 576-Mbit/s 64-QAM 4 × 4 MIMO Precoding Processor With Lattice Reduction.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Loop-Reduction LLL Algorithm and Architecture for Lattice-Reduction-Aided MIMO Detection.
J. Electr. Comput. Eng., 2012
A constant-throughput LLL algorithm with deep insertion for LR-aided MIMO detection.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Low-complexity lattice reduction architecture using interpolation-based QR decomposition for MIMO-OFDM systems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
Power-Saving 4 ˟ 4 Lattice-Reduction Processor for MIMO Detection With Redundancy Checking.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Latency-constrained low-complexity lattice reduction for MIMO-OFDM systems.
Proceedings of the IEEE International Conference on Acoustics, 2011
A 684Mbps 57mW joint QR decomposition and MIMO processor for 4×4 MIMO-OFDM systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
Design of 4 × 4 MIMO-OFDMA receiver with precode codebook search for 3GPP-LTE.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Multi-stage lattice-reduction-aided MIMO detector using reverse-order LLL algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010