A Highly Efficient 165-GHz 4FSK 17-Gb/s Transceiver System With Frequency Overlapping Architecture in 65-nm CMOS.

Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC.

A 0.19 mm² 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS.

Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC.

60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration.