Programming Models for Determining Optimal R&D Arrangement in Mobile Application Development Process.
IEEE Access, 2022
A novel configuration context cache structure of reconfigurable systems.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor.
IEEE Trans. Signal Process., 2013
A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Dynamic Allocation of SPM Based on Time-Slotted Cache Conflict Graph for System Optimization.
IEICE Trans. Inf. Syst., 2012
Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst., 2012
Exploration of Full HD Media Decoding on SDR Baseband Processor.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012