Deep Learning-Enabled Swallowing Monitoring and Postoperative Recovery Biosensing System.
CoRR, 2023
A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro.
IEEE J. Solid State Circuits, 2013
An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.
IEEE J. Solid State Circuits, 2013
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.
,
,
,
,
,
,
,
,
,
,
,
,
,
,
IEEE J. Solid State Circuits, 2013
Degradation algorithm of compressive sensing for integer DCT with application to H. 264/AVC.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013
Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications.
IEEE J. Solid State Circuits, 2012
A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
,
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory.
,
,
,
,
,
,
,
,
,
,
,
,
Proceedings of the IEEE International Solid-State Circuits Conference, 2011