2024
A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture.
IEEE J. Solid State Circuits, August, 2024

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

2023
A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023