13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate.
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Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Multi-object Tracking from the Classics to the Modern.
PhD thesis, 2022
Design of 36 dB IRR baseband analog for Bluetooth low energy 5.0 application in 55 nm CMOS.
Proceedings of the International SoC Design Conference, 2017
Design of filter tuning circuit to compensate band width change of band pass filter by process and temperature.
Proceedings of the International SoC Design Conference, 2017
Varactor tuned ring resonator filter with wide tunable bandwidth.
Proceedings of the 2015 IEEE Radio and Wireless Symposium, 2015
High-Voltage Analog System for a Mobile NAND Flash.
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IEEE J. Solid State Circuits, 2008