A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Scalable High-Radix Modular Crossbar Switches.
Proceedings of the 24th IEEE Annual Symposium on High-Performance Interconnects, 2016
Modeling and Design of High-Radix On-Chip Crossbar Switches.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
DELPHI: a framework for RTL-based architecture design evaluation using DSENT models.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015
High-efficiency crossbar switches using capacitively coupled signaling.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012
6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses.
Proceedings of the HOST 2010, 2010