2019
Subsystem under 3D-Storage Class Memory on a chip.
Comput. Electr. Eng., 2019

2017
Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM.
IEEE Trans. Computers, 2017

Erratum: CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction [IEICE Electronics Express Vol. 14 (2017) No. 10 pp. 20170053].
IEICE Electron. Express, 2017

CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction.
IEICE Electron. Express, 2017

Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process.
IEICE Electron. Express, 2017

Multi-core architecture with asynchronous clocks to prevent power analysis attacks.
IEICE Electron. Express, 2017

2016
A 40-nm 16-Mb Contact-Programming Mask ROM Using Dual Trench Isolation Diode Bitcell.
IEEE Trans. Very Large Scale Integr. Syst., 2016

An FPGA enhanced extensible and parallel query storage system for emerging NVRAM.
IEICE Electron. Express, 2016

2007
Multilevel Storage in Phase-Change Memory.
IEICE Trans. Electron., 2007

2006
Electronic properties of GST for non-volatile memory.
Microelectron. J., 2006

Characterization of Ge<sub>2</sub>Sb<sub>2</sub>Te<sub>5</sub> thin film transistor and its application in non-volatile memory.
Microelectron. J., 2006