On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Efficient Timing Analysis With Known False Paths Using Biclique Covering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
The Y architecture for on-chip interconnect: analysis and methodology.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Unified quadratic programming approach for mixed mode placement.
Proceedings of the 2005 International Symposium on Physical Design, 2005
Improving the efficiency of static timing analysis with false paths.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Integrated algorithmic logical and physical design of integer multiplier.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Floorplan Representation in VLSI.
Proceedings of the Handbook of Data Structures and Applications., 2004
A multiple level network approach for clock skew minimization with process variations.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Floorplan representations: Complexity and connections.
ACM Trans. Design Autom. Electr. Syst., 2003
A hierarchical three-way interconnect architecture for hexagonal processors.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003
Power network analysis using an adaptive algebraic multigrid approach.
Proceedings of the 40th Design Automation Conference, 2003
An algebraic multigrid solver for analytical placement with layout based clustering.
Proceedings of the 40th Design Automation Conference, 2003
The Y-architecture: yet another on-chip interconnect solution.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Physical Planning Of On-Chip Interconnect Architectures.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
Revisiting floorplan representations.
Proceedings of the 2001 International Symposium on Physical Design, 2001