A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.
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IEEE J. Solid State Circuits, January, 2024
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.
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Proceedings of the IEEE International Solid- State Circuits Conference, 2023
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.
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Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface.
Proceedings of the International SoC Design Conference, 2018