2025
Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2025
2024
MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors.
Microprocess. Microsystems, 2024
Circumventing Restrictions in Commercial High-Level Synthesis Tools.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Application Specific Approximate Behavioral Processor.
IEEE Trans. Sustain. Comput., 2023
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis.
Integr., 2023
I-TAINTED: Identification of Turmeric Adulteration Using the CavIty PerturbatioN Technique and Technology OptimizED Machine Learning.
IEEE Access, 2023
CERTIFY: AutomatiC MEasuRing The QualIty oF High-Level SYnthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
ADVICE: Automatic Design and Optimization of Behavioral Application Specific Processors.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
PEPA: Performance Enhancement of Embedded Processors through HW Accelerator Resource Sharing.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Approximating HW Accelerators through Partial Extractions onto Shared Artificial Neural Networks.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs.
ACM Trans. Design Autom. Electr. Syst., 2022
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control.
ACM Trans. Design Autom. Electr. Syst., 2022
SSSL: Secure Search Space Locking of Behavioral IPs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Predictive Model Attack for Embedded FPGA Logic Locking.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Modernizing Hardware Circuits through High-Level Synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Fast Parallel High-Level Synthesis Design Space Explorer: Targeting FPGAs to accelerate ASIC Exploration.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Optimizing Behavioral Near On-Chip Memory Computing Systems.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022
Source Code Obfuscation of Behavioral IPs: Challenges and Solutions.
Behavioral Synthesis for Hardware Security, 2022
2021
Efficient Hierarchical Post-Silicon Validation and Debug.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
Micro-architecture Tuning for Dynamic Frequency Scaling in Coarse-Grain Runtime Reconfigurable Arrays with Adaptive Clock Domain Support.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
BEACON: BEst Approximations for Complete BehaviOral HeterogeNeous SoCs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Functional Locking through Omission: From HLS to Obfuscated Design.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Special Session: ADAPT: ANN-ControlleD System-Level Runtime Adaptable APproximate CompuTing.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
Unlocking Approximations through Selective Source Code Transformations.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Locking the Re-usability of Behavioral IPs: Discriminating the Search Space through Partial Encryptions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Watermarking of Behavioral IPs: A Practical Approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Enabling the Design of Behavioral Systems-on-Chip.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
High-Level Synthesis Design Space Exploration: Past, Present, and Future.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Predictive Compositional Method to Design and Reoptimize Complex Behavioral Dataflows.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Efficient Functional Locking of Behavioral IPs.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Light-Weight Soft-Errors Detection Mechanism in High-Level Synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Bespoke Behavioral Processors.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020
On the Design of High Performance HW Accelerator through High-level Synthesis Scheduling Approximations.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterization.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Toward Self-Tunable Approximate Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Design space exploration of heterogeneous MPSoCs with variable number of hardware accelerators.
Microprocess. Microsystems, 2019
<i>VeriIntel2C</i>: Abstracting RTL to C to maximize High-Level Synthesis Design Space Exploration.
Integr., 2019
VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks.
IEICE Trans. Inf. Syst., 2019
Optimizing RTL to C Abstraction Methodologies to Improve HLS Design Space Exploration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Learning-Based Diversity Estimation: Leveraging the Power of High-Level Synthesis to Mitigate Common-Mode Failure.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Exploiting the Benefits of High-Level Synthesis for Thermal-Aware VLSI Design.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Low Power Design through Frequency-Optimized Runtime Micro-Architectural Adaptation.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models.
Proceedings of the International Conference on Computer-Aided Design, 2019
Exploring Design Trade-offs in Fault-Tolerant Behavioral Hardware Accelerators.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Thermal Fingerprinting of FPGA Designs through High-Level Synthesis.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
Partial Encryption of Behavioral IPs to Selectively Control the Design Space in High-Level Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Common-Mode Failure Mitigation: Increasing Diversity through High-Level Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space Exploration.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Accelerating cycle-accurate system-level simulations through behavioral templates.
Integr., 2018
Control Flow Checking Optimization Based on Regular Patterns Analysis.
Proceedings of the 23rd IEEE Pacific Rim International Symposium on Dependable Computing, 2018
Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable Architectures.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Autonomous Temperature Management through Selective Control of Exact-Approximate Tiles.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Investigation and Optimization of Pin Multiplexing in High-Level Synthesis.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
A machine learning based hard fault recuperation model for approximate hardware accelerators.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies.
ACM Trans. Design Autom. Electr. Syst., 2017
Hardware Trojan Detection in Behavioral Intellectual Properties (IP's) Using Property Checking Techniques.
IEEE Trans. Emerg. Top. Comput., 2017
Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
S3CBench: Synthesizable Security SystemC Benchmarks for High-Level Synthesis.
J. Hardw. Syst. Secur., 2017
Trust Filter: Runtime Hardware Trojan Detection in Behavioral MPSoCs.
J. Hardw. Syst. Secur., 2017
Characterization and optimization of behavioral hardware accelerators in heterogeneous MPSoCs.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017
HW/SW co-design experimental framework using configurable SoCs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Efficient behavioral intellectual properties source code obfuscation for high-level synthesis.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Configurable SoC In-Situ Hardware/Software Co-Design Design Space Exploration.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic Workloads.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
What to Lock?: Functional and Parametric Locking.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Learning-based interconnect-aware dataflow accelerator optimization.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case Study.
Proceedings of the Euromicro Conference on Digital System Design, 2017
2016
Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Source Code Error Detection in High-Level Synthesis Functional Verification.
IEEE Trans. Very Large Scale Integr. Syst., 2016
Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Implementation of a FPGA-Based Feature Detection and Networking System for Real-time Traffic Monitoring.
CoRR, 2016
On Time Redundancy of Fault Tolerant C-Based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
Optimization of behavioral IPs in multi-processor system-on-chips.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Hierarchical High-Level Synthesis Design Space Exploration with Incremental Exploration Support.
IEEE Embed. Syst. Lett., 2015
Temperature-triggered behavioral IPs HW Trojan detection method with FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
2014
S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis.
IEEE Embed. Syst. Lett., 2014
Time sharing of Runtime Coarse-Grain Reconfigurable Architectures processing elements in multi-process systems.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
HW acceleration of multiple applications on a single FPGA.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Allocation of FPGA DSP-macros in multi-process high-level synthesis systems.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2012
Divide and conquer high-level synthesis design space exploration.
ACM Trans. Design Autom. Electr. Syst., 2012
Machine learning predictive modelling high-level synthesis design space exploration.
IET Comput. Digit. Tech., 2012
2011
Precision tunable RTL macro-modelling cycle-accurate power estimation.
IET Comput. Digit. Tech., 2011
2010
Design Space Exploration Acceleration Through Operation Clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Semi-Automatic Control Unit Generation for Complex VLSI Designs.
IPSJ Trans. Syst. LSI Des. Methodol., 2010
Fixed Point Data Type Modeling for High Level Synthesis.
IEICE Trans. Electron., 2010
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Design of complex image processing systems in ESL.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Autonomous temperature control technique in VLSI circuits through logic replication.
IET Comput. Digit. Tech., 2009
2008
Hotspots Elimination and Temperature Flattening in VLSI Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2008
2007
Temperature-Aware Compilation for VLIWProcessors.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007
2003
Acceleration of the discrete element method on a reconfigurable co-processor.
PhD thesis, 2003
2002
Scalable Implementation of the Discrete Element Method on a Reconfigurable Computing Platform.
Proceedings of the Field-Programmable Logic and Applications, 2002
Analysis and Implementation of the Discrete Element Method Using a Dedicated Highly Parallel Architecture in Reconfigurable Computing.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002
2001
Evaluation of an FPGA Implementation of the Discrete Element Method.
Proceedings of the Field-Programmable Logic and Applications, 2001