2014

Early detection and repair of VRT and aging DRAM bits by margined in-field BIST.

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2014

2013

An Intelligent RAM with Serial I/Os.

[DOI]

Jayaprakash Balachandran

IEEE Micro, 2013

2012

A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications.

[DOI]

Socrates D. Vamvakos

Claude R. Gauthier

Chethan Rao

Karthisha Ramoshan Canagasaby

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency.

[DOI]

Proceedings of the 38th European Solid-State Circuit conference, 2012

2003

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells.

[DOI]

IEEE J. Solid State Circuits, 2003

On-Chip Interconnect Inductance - Friend or Foe (Invited).

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002

High-frequency characterization of on-chip digital interconnects.

[DOI]

IEEE J. Solid State Circuits, 2002

Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design".

[DOI]

IEEE J. Solid State Circuits, 2002

2001

Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design.

[DOI]

IEEE J. Solid State Circuits, 2001