A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer.
IEICE Electron. Express, 2018
A 4 GS/s 6-bit 4-2 segmented current-steering DAC with compact current cells.
IEICE Electron. Express, 2018
A 12GS/s 6-bit DAC with 4-2 Segmentation in 40nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Duty Cycle Distortion in Half-rate Nyquist DACs with Limited Output Bandwidth.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 6-bit 700-MS/s single-channel SAR ADC with low kickback noise comparator in 40-nm CMOS.
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Auxiliary testability design schemes for CMOS DACs with ultrahigh sampling rates.
Proceedings of the 12th IEEE International Conference on ASIC, 2017