A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend.
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IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics.
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Proceedings of the 47th ESSCIRC 2021, 2021
Continuous-time linear equalizer with automatic boosting gain adaptation and input offset cancellation.
Int. J. Circuit Theory Appl., 2018