Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture.
PhD thesis, 2016
Zero-load predictive model for performance analysis in deflection routing NoCs.
Microprocess. Microsystems, 2015
Automated Power and Latency Management in Heterogeneous 3D NoCs.
Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015
Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Dark silicon aware power management for manycore systems under dynamic workloads.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks.
Proceedings of the NOCS 2011, 2011
Scalability of network-on-chip communication architecture for 3-D meshes.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
3-D memory organization and performance analysis for multi-processor network-on-chip architecture.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.
Proceedings of the IEEE International Conference on 3D System Integration, 2009