2023
Machine Learning-Based Adaptive Outlier Detection for Underkill Reduction in Analog/RF IC Testing.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
2022
Machine Learning-Based Overkill Reduction through Inter-Test Correlation.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
2019
Wafer-Level Adaptive Vmin Calibration Seed Forecasting.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Special session on machine learning: How will machine learning transform test?
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
2017
Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Wafer-level adaptive trim seed forecasting based on E-tests.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Wafer-level process variation-driven probe-test flow selection for test cost reduction in analog/RF ICs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Statistical outlier screening as a test solution health monitor.
Proceedings of the 2016 IEEE International Test Conference, 2016
What we know after twelve years developing and deploying test data analytics solutions.
Proceedings of the 2016 IEEE International Test Conference, 2016
Harnessing process variations for optimizing wafer-level probe-test flow.
Proceedings of the 2016 IEEE International Test Conference, 2016
Harnessing fabrication process signature for predicting yield across designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A machine learning approach to fab-of-origin attestation.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
2015
Yield prognosis for fab-to-fab product migration.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2014
IC laser trimming speed-up through wafer-level spatial correlation modeling.
Proceedings of the 2014 International Test Conference, 2014
2013
Predicting die-level process variations from wafer test data for analog devices: A feasibility study.
Proceedings of the 14th Latin American Test Workshop, 2013
2011
Die-level adaptive test: Real-time test reordering and elimination.
Proceedings of the 2011 IEEE International Test Conference, 2011
2010
Adapting to adaptive testing.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Statistics in Semiconductor Test: Going beyond Yield.
IEEE Des. Test Comput., 2009
Multidimensional Test Escape Rate Modeling.
IEEE Des. Test Comput., 2009
Quality improvement and cost reduction using statistical outlier methods.
Proceedings of the 27th International Conference on Computer Design, 2009
2005
Burn-in reduction using principal component analysis.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005