2022
Convolutional neural network implementations using Vitis AI.
Proceedings of the 12th IEEE Annual Computing and Communication Workshop and Conference, 2022
2018
Acceleration of Analysis Processing on Decentralized Performance Profiling System Using Virtual Machines.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018
2007
Network Processor for High-Speed Network and Quick Programming.
J. Circuits Syst. Comput., 2007
2004
Dynamically Reconfigurable Logic LSI: PCA-2.
IEICE Trans. Inf. Syst., 2004
2003
Concept and implementation of run-time resource management system operating on autonomously reconfigurable architecture.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA.
Proceedings of the Advances in Computer Systems Architecture, 2003
2002
A Method of Mapping Finite State Machine into PCA Plastic Parts.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
2001
Solving satisfiability problems using reconfigurable computing.
IEEE Trans. Very Large Scale Integr. Syst., 2001
Self-reorganising systems on VLSI circuits.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Scalable space/time-shared stream-processing on the run-time reconfigurable PCA architecture.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
2000
SPFD: A new method to express functional flexibility.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture.
Proceedings of the Field-Programmable Logic and Applications, 2000
A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology.
Proceedings of the Field-Programmable Logic and Applications, 2000
An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation.
Proceedings of ASP-DAC 2000, 2000
1999
Summation Algorithms on Constrained Reconfigurable Meshes.
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999
Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic.
Proceedings of the Parallel and Distributed Processing, 1999
An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture.
Proceedings of the Parallel and Distributed Processing, 1999
An Integrated Approach for Synthesizing LUT Networks.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
A Method for Implementing Fractal Image Compression on Reconfigurable Architecture.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999
Solving Satisfiability Problems on FPGAs Using Experimental Unit Propagation.
Proceedings of the Principles and Practice of Constraint Programming, 1999
Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998
Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions.
Proceedings of the 1998 Design, 1998
New Methods to Find Optimal Non-Disjoint Bi-Decompositions.
Proceedings of the ASP-DAC '98, 1998
1997
Formulation of the Addition-Shift-Sequence Problem and Its Complexity.
Proceedings of the Algorithms and Computation, 8th International Symposium, 1997
Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997
1996
LUT-based FPGA Technology Mapping using Permissible Functions.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
A new method to express functional permissibilities for LUT based FPGAs and its applications.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
1995
Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
1990
Multi-Level Optimization for Large Scale ASICS.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990