A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin.
IEEE J. Solid State Circuits, 2018
A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Changes in the fluctuation of interbeat intervals in spontaneously beating cultured cardiac myocytes: experimental and modeling studies.
Biol. Cybern., 2002