Austin Rovinski
Orcid: 0000-0003-1761-1898
According to our database1,
Austin Rovinski
authored at least 13 papers
between 2015 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
CoRR, 2024
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
2020
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
IEEE J. Solid State Circuits, 2020
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
2019
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro, 2018
2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017
2016
Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant.
ACM Trans. Comput. Syst., 2016
2015
Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015