Augustus K. Uht

Orcid: 0000-0002-8652-1960

According to our database1, Augustus K. Uht authored at least 27 papers between 1986 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Fast Key-Value Lookups with Node Tracker.
ACM Trans. Archit. Code Optim., 2021

2020
Exploring Prefetching, Pre-Execution and Branch Outcome Streaming for In-Memory Database Lookups.
IEEE Comput. Archit. Lett., 2020

2009
Central vs. distributed dynamic thermal management for multi-core processors: which one is better?
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2007
The impact of wrong-path memory references in cache-coherent multiprocessor systems.
J. Parallel Distributed Comput., 2007

2006
Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control.
IEEE Trans. Computers, 2005

2004
Going Beyond Worst-Case Specs with TEAtime.
Computer, 2004

2003
Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture.
SIGARCH Comput. Archit. News, 2003

Levo - A Scalable Processor With High IPC.
J. Instr. Level Parallelism, 2003

2002
Disjoint Eager Execution: what it is / what it is not.
SIGARCH Comput. Archit. News, 2002

Realizing High IPC Using Time-Tagged Resource-Flow Computing.
Proceedings of the Euro-Par 2002, 2002

2000
Building Real Computer Systems.
IEEE Micro, 2000

1998
The integrated computer engineering design (ICED) curriculum.
Proceedings of the 1998 workshop on Computer architecture education, 1998

1997
Branch Effect Reduction Techniques.
Computer, 1997

1995
Disjoint eager execution: an optimal form of speculative execution.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1993
Extraction of massive instruction level parallelism.
SIGARCH Comput. Archit. News, 1993

1992
Requirements for Optimal Execution of Loops with Tests.
IEEE Trans. Parallel Distributed Syst., 1992

Concurrency Extraction via Hardware Methods Executing the Static Instruction Stream.
IEEE Trans. Computers, 1992

Data path issues in a highly concurrent machine.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

1991
A Theory of Reduced and Minimal Procedural Dependencies.
IEEE Trans. Computers, 1991

1990
Ideograph/Ideogram: framework/hardware for eager evaluation.
Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

1989
Program Optimization with Ideograph.
Proceedings of the International Conference on Parallel Processing, 1989

1988
Modeling the effects of instruction queue loading on a static instruction stream micro-architecture.
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

Requirements for optimal execution ofL oops with tests.
Proceedings of the 2nd international conference on Supercomputing, 1988

1987
On the combination of hardware and software concurrency extraction methods.
Proceedings of the 20st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1987

Incremental Performance Contributions of Hardware Concurrency Extraction Techniques.
Proceedings of the Supercomputing, 1987

1986
Hardware Extraction of Low-Level Concurrency from Serial Instruction Streams.
Proceedings of the International Conference on Parallel Processing, 1986


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