Aubin Roy

According to our database1, Aubin Roy authored at least 12 papers between 1999 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan.
IEEE Des. Test Comput., 2012

2011
Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan.
Proceedings of the 2011 IEEE International Test Conference, 2011

A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution.
Proceedings of the 16th European Test Symposium, 2011

2008
Noise-Insensitive Digital BIST for any PLL or DLL.
J. Electron. Test., 2008

2007
A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes.
Proceedings of the 2007 IEEE International Test Conference, 2007

Purely Digital BIST for Any PLL or DLL.
Proceedings of the 12th European Test Symposium, 2007

Testing SerDes beyond 4 Gbps - changing priorities.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005
Structural tests for jitter tolerance in SerDes receivers.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz.
IEEE Des. Test Comput., 2004

An Automated, Complete, Structural Test Solution for SERDES.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002
High Accuracy Stimulus Generation for A/D Converter BIST.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

1999
BIST for phase-locked loops in digital applications.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999


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