Atsutake Kosuge
Orcid: 0000-0002-3394-2227
According to our database1,
Atsutake Kosuge
authored at least 49 papers
between 2012 and 2024.
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Bibliography
2024
A 0.13mJ/Prediction CIFAR-100 Fully Synthesizable Raster-Scan-Based Wired-Logic Processor in 16-nm FPGA.
IEICE Trans. Electron., 2024
Efficient FPGA Resource Utilization in Wired-Logic Processors Using Coarse and Fine Segmentation of LUTs for Non-Linear Functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
Crosstalk Analysis and Countermeasures of High-Bandwidth 3D-Stacked Memory Using Multi-Hop Inductive Coupling Interface.
IEICE Trans. Electron., July, 2023
A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum.
IEEE Micro, 2023
A 7-nm FinFET 1.2-TB/s/mm<sup>2</sup> 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver.
IEEE J. Solid State Circuits, 2023
A 183.4nJ/inference 152.8μW Single-Chip Fully Synthesizable Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Analysis and Design of a 7 Gb/s Rotatable Non-contact Connector with Grid Array Package Application.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
An Occlusion-Resilient mmWave Imaging Radar-Based Object Recognition System Using Synthetic Training Data Generation Technique.
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023
A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-Linear Function Blocks in 0.18μm CMOS.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
mmWave-YOLO: A mmWave Imaging Radar-Based Real-Time Multiclass Object Recognition System for ADAS Applications.
IEEE Trans. Instrum. Meas., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network.
IEEE Open J. Circuits Syst., 2022
A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC.
IEEE J. Solid State Circuits, 2022
A 6.5Gb/s Shared Bus Using Electromagnetic Connectors for Downsizing and Lightening Satellite Processor System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
An Anomaly Detection System for Transparent Objects Using Polarized-Image Fusion Technique.
Proceedings of the IEEE Sensors Applications Symposium, 2022
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
A 7 Gb/s Micro Rotatable Transmission Line Coupler with Deep Proximity Coupling Mode and Ground Shielding Vias.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A Low-power RFID with 100kbps Data Rate Employing High-speed Power Clock Generator for Complementary Pass-transistor Adiabatic Logic.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
A 7-nm FinFET 1.2-TB/s/mm<sup>2</sup> 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022
A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
POISON: Human Pose Estimation in Insufficient Lighting Conditions Using Sensor Fusion.
IEEE Trans. Instrum. Meas., 2021
An SoC-FPGA-Based Iterative-Closest-Point Accelerator Enabling Faster Picking Robots.
IEEE Trans. Ind. Electron., 2021
A 16 nJ/Classification FPGA-Based Wired-Logic DNN Accelerator Using Fixed-Weight Non-Linear Neural Net.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
A 5-GHz 0.15-mm<sup>2</sup> Collision Avoidable RFID Employing Complementary Pass-transistor Adiabatic Logic with an Inductively Connected External Antenna.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 1200×1200 8-Edges/Vertex FPGA-Based Motion-Planning Accelerator for Dual-Arm-Robot Manipulation Systems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
An Object-Pose Estimation Acceleration Technique for Picking Robot Applications by Using Graph-Reusing k-NN Search.
Proceedings of the First International Conference on Graph Computing, 2019
A 4.8x Faster FPGA-Based Iterative Closest Point Accelerator for Object Pose Estimation of Picking Robot Applications.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
2016
A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver.
IEEE J. Solid State Circuits, 2016
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories.
IEEE J. Solid State Circuits, 2016
Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO.
IEICE Trans. Electron., 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Inductively-powered wireless solid-state drive (SSD) system with merged error correction of high-speed non-contact data links and NAND flash memory.
Proceedings of the Symposium on VLSI Circuits, 2015
10.1 A 6Gb/s 6pJ/b 5mm-distance non-contact interface for modular smartphones using two-fold transmission-line coupler and EMC-qualified pulse transceiver.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
24.4 A 6.5Gb/s Shared bus using electromagnetic connectors for downsizing and lightening satellite processor system by 60%.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE J. Solid State Circuits, 2014
30.6 An electromagnetic clip connector for in-vehicle LAN to reduce wire harness weight by 30%.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 12.5Gb/s/link non-contact multi drop bus system with impedance-matched transmission line couplers and Dicode partial-response channel transceivers.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012