Atsushi Takahashi

Orcid: 0000-0003-3821-5325

Affiliations:
  • Tokyo Institute of Technology


According to our database1, Atsushi Takahashi authored at least 77 papers between 1992 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
Two-layer Bottleneck Channel Track Assignment for Analog VLSI.
IPSJ Trans. Syst. LSI Des. Methodol., 2024

BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Report on the 28th Asia and South Pacific Design Automation Conference.
IEEE Des. Test, June, 2023

2020
Message from the Editor-in-Chief.
IPSJ Trans. Syst. LSI Des. Methodol., 2020

A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2019
A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017
A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement.
IPSJ Trans. Syst. LSI Des. Methodol., 2017

A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016
A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Manufacturability-aware mask assignment in multiple patterning lithography.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A Length Matching Routing Algorithm for Set-Pair Routing Problem.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Effective two-dimensional pattern generation for self-aligned double patterning.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography.
Proceedings of the Algorithms and Computation - 25th International Symposium, 2014

A fast process variation and pattern fidelity aware mask optimization algorithm.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2-SAT based linear time optimum two-domain clock skew scheduling.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization.
IPSJ Trans. Syst. LSI Des. Methodol., 2013

Dawn of computer-aided design: from graph-theory to place and route.
Proceedings of the International Symposium on Physical Design, 2013

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
An any-angle routing method using quasi-Newton method.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Single-Layer Trunk Routing Using Minimal 45-Degree Lines.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

RRA-based multi-objective optimization to mitigate the worst cases of placement.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009
Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008
A Fast Clock Scheduling for Peak Power Reduction in LSI.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

A semi-monotonic routing method for fanin type Ball Grid Array packages.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Practical Fast Clock-Schedule Design Algorithms.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Monotonic parallel and orthogonal routing for single-layer ball grid array packages.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Low area pipelined circuits by multi-clock cycle paths and clock scheduling.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A global routing method for 2-layer ball grid array packages.
Proceedings of the 2005 International Symposium on Physical Design, 2005

2004
Optimal integer delay-budget assignment on directed acyclic graphs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Incremental Timing Budget Management in Programmable Systems.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003
Optimal integer delay budgeting on directed acyclic graphs.
Proceedings of the 40th Design Automation Conference, 2003

2002
A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A Semi-Synchronous Circuit Design Method by Clock Tree Modification.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Delay variation tolerant clock scheduling for semi-synchronous circuits.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
Clustering based fast clock scheduling for light clock-tree.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A practical clock tree synthesis for semi-synchronous circuits.
Proceedings of the 2000 International Symposium on Physical Design, 2000

1999
Enumerating the min-cuts for applications to graph extraction under size constraints.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Air-Pressure-Model-Based Fast Algorithms for General Floorplan.
Proceedings of the ASP-DAC '98, 1998

1997
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Performance and reliability driven clock scheduling of sequential logic circuits.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Detailed-Routability of FPGAs with Extremal Switch-Block Structures.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Mixed Searching and Proper-Path-Width.
Theor. Comput. Sci., 1995

1994
Minimal acyclic forbidden minors for the family of graphs with bounded path-width.
Discret. Math., 1994

1992
Peel-the-box: a concept of switch-box routing and tractable problems.
Integr., 1992


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