Atsushi Takahashi

According to our database, Atsushi Takahashi authored at least 77 papers between 1992 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Two-layer Bottleneck Channel Track Assignment for Analog VLSI.

Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka

IPSJ Trans. Syst. LSI Des. Methodol., 2024

BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem.

Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

Report on the 28th Asia and South Pacific Design Automation Conference.

Atsushi Takahashi

IEEE Des. Test, June, 2023

2020

Message from the Editor-in-Chief.

Atsushi Takahashi

IPSJ Trans. Syst. LSI Des. Methodol., 2020

A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections.

Shimpei Sato, Kano Akagi, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

2019

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution.

Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution.

Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses.

Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017

A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling.

Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama

IEEE Trans. Very Large Scale Integr. Syst., 2017

Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement.

Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama

IPSJ Trans. Syst. LSI Des. Methodol., 2017

A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning.

Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model.

Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern.

Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation.

Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Manufacturability-aware mask assignment in multiple patterning lithography.

Yukihide Kohira, Atsushi Takahashi, Tomomi Matsui, Chikaaki Kodama, Shigeki Nojima, Satoshi Tanaka

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods.

Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima, Shigeki Nojima, Toshiya Kotani, Takeshi Ihara, Atsushi Takahashi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

A Length Matching Routing Algorithm for Set-Pair Routing Problem.

Yuta Nakatani, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Effective two-dimensional pattern generation for self-aligned double patterning.

Takeshi Ihara, Atsushi Takahashi, Chikaaki Kodama

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography.

Yukihide Kohira, Tomomi Matsui, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization.

Yiqiang Sheng, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography.

Tomomi Matsui, Yukihide Kohira, Chikaaki Kodama, Atsushi Takahashi

Proceedings of the Algorithms and Computation - 25th International Symposium, 2014

A fast process variation and pattern fidelity aware mask optimization algorithm.

Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2-SAT based linear time optimum two-domain clock skew scheduling.

Yukihide Kohira, Atsushi Takahashi

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization.

Yiqiang Sheng, Atsushi Takahashi

IPSJ Trans. Syst. LSI Des. Methodol., 2013

Dawn of computer-aided design: from graph-theory to place and route.

Atsushi Takahashi

Proceedings of the International Symposium on Physical Design, 2013

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control.

Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto, Atsushi Takahashi

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

An any-angle routing method using quasi-Newton method.

Yukihide Kohira, Atsushi Takahashi

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Foreword.

Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Single-Layer Trunk Routing Using Minimal 45-Degree Lines.

Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement.

Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

RRA-based multi-objective optimization to mitigate the worst cases of placement.

Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009

Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages.

Yoichi Tomioka, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages.

Yoichi Tomioka, Yoshiaki Kurata, Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework.

Yukihide Kohira, Shuhei Tani, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound.

Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

A Fast Clock Scheduling for Peak Power Reduction in LSI.

Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems.

Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages.

Yoichi Tomioka, Atsushi Takahashi

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

A semi-monotonic routing method for fanin type Ball Grid Array packages.

Yoichi Tomioka, Atsushi Takahashi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements.

Bakhtiar Affendi Rosdi, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework.

Yukihide Kohira, Atsushi Takahashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages.

Yukiko Kubo, Atsushi Takahashi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages.

Yoichi Tomioka, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Practical Fast Clock-Schedule Design Algorithms.

Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits.

Bakhtiar Affendi Rosdi, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.

Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Monotonic parallel and orthogonal routing for single-layer ball grid array packages.

Yoichi Tomioka, Atsushi Takahashi

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Low area pipelined circuits by multi-clock cycle paths and clock scheduling.

Bakhtiar Affendi Rosdi, Atsushi Takahashi

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits.

Bakhtiar Affendi Rosdi, Atsushi Takahashi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages.

Yukiko Kubo, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

A global routing method for 2-layer ball grid array packages.

Yukiko Kubo, Atsushi Takahashi

Proceedings of the 2005 International Symposium on Physical Design, 2005

2004

Optimal integer delay-budget assignment on directed acyclic graphs.

Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Incremental Timing Budget Management in Programmable Systems.

Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003

Optimal integer delay budgeting on directed acyclic graphs.

Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh

Proceedings of the 40th Design Automation Conference, 2003

2002

A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees.

Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling.

Keiichi Kurokawa, Takuya Yasui, Yoichi Matsumura, Masahiko Toyonaga, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

A Semi-Synchronous Circuit Design Method by Clock Tree Modification.

Seiichiro Ishijima, Tetsuaki Utsumi, Tomohiro Oto, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm.

Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Delay variation tolerant clock scheduling for semi-synchronous circuits.

Hidetoshi Matsumura, Atsushi Takahashi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Clustering based fast clock scheduling for light clock-tree.

Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Partition, Packing and Clock Distribution-A New Paradigm of Physical Design.

Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A practical clock tree synthesis for semi-synchronous circuits.

Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi

Proceedings of the 2000 International Symposium on Physical Design, 2000

1999

Enumerating the min-cuts for applications to graph extraction under size constraints.

Kengo R. Azegami, Atsushi Takahashi, Y. Kajitan

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion.

Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998

Air-Pressure-Model-Based Fast Algorithms for General Floorplan.

Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani

Proceedings of the ASP-DAC '98, 1998

1997

Clock-tree routing realizing a clock-schedule for semi-synchronous circuits.

Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Performance and reliability driven clock scheduling of sequential logic circuits.

Atsushi Takahashi, Yoji Kajitani

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Detailed-Routability of FPGAs with Extremal Switch-Block Structures.

Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Mixed Searching and Proper-Path-Width.

Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani

Theor. Comput. Sci., 1995

1994

Minimal acyclic forbidden minors for the family of graphs with bounded path-width.

Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani

Discret. Math., 1994

1992

Peel-the-box: a concept of switch-box routing and tractable problems.

Atsushi Takahashi, Yoji Kajitani

Integr., 1992