Atsushi Maeda

According to our database, Atsushi Maeda authored at least 12 papers between 1987 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2012

Changes that modularization makes in antenna design.

Atsushi Maeda, Keiichi Ohizumi

Proceedings of the Seventh International Conference on Digital Information Management, 2012

2000

3D Viewpoint Selection and Bilateral Control for Bio-Micromanipulation.

Fumihito Arai, Tomohiko Sugiyama, Poom Luangjarmekorn, Akiko Kawaji, Toshio Fukuda, Kouichi Itoigawa, Atsushi Maeda

Proceedings of the 2000 IEEE International Conference on Robotics and Automation, 2000

1996

Performance analysis of parallel garbage collection using partial marking.

Yoshio Tanaka, Atsushi Maeda, Masakazu Nakanishi, Shogo Matsui

Syst. Comput. Jpn., 1996

1995

Complementary Garbage Collector

Shogo Matsui, Yoshio Tanaka, Atsushi Maeda, Masakazu Nakanishi

Proceedings of the Memory Management, 1995

1994

Partial Marking GC.

Yoshio Tanaka, Shogo Matsui, Atsushi Maeda, Masakazu Nakanishi

Proceedings of the Parallel Processing: CONPAR 94, 1994

1992

A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses.

Yutaka Arima, Mitsuhiro Murasaki, Tsuyoshi Yamada, Atsushi Maeda, Hirofumi Shinohara

IEEE J. Solid State Circuits, December, 1992

1991

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture.

Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Hiromi Notani, Harufusa Kondoh, Shinpei Kayano

IEEE J. Solid State Circuits, November, 1991

A 10-b 70-MS/s CMOS D/A converter.

Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh, Nobuharu Yazawa

IEEE J. Solid State Circuits, April, 1991

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses.

Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Harufusa Kondoh, Shimpei Kayano

IEEE J. Solid State Circuits, April, 1991

1990

A 30-MHz mixed analog/digital signal processor.

Sumitaka Takeuchi, Hiroyuki Kouno, Yoshinori Hayashi, Atsushi Maeda, Keisuke Okada, Nobuharu Yazawa

IEEE J. Solid State Circuits, December, 1990

An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption.

Shiro Hosotani, Takahiro Miki, Atsushi Maeda, Nobuharu Yazawa

IEEE J. Solid State Circuits, February, 1990

1987

SYNAPSE: A Multi-Microprocessor Lisp Machine with Parallel Garbage Collector.

Shogo Matsui, Yoshinobu Kato, Shinsuke Teramura, Tomoyuki Tanaka, Nobuyuki Mohri, Atsushi Maeda, Masakazu Nakanishi

Proceedings of the Parallel Algorithms and Architectures, 1987