Atsushi Iwata

According to our database, Atsushi Iwata authored at least 88 papers between 1982 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

CMOS Gaussian Monocycle Pulse Transceiver for Radar-Based Microwave Imaging.

Takamaro Kikkawa, Yoshihiro Masui, Akihiro Toya, Hiroyuki Ito, Takuichi Hirano, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Tsuyoshi Matsumaru, Michimasa Yamaguchi, Mitsutoshi Sugawara, Afreen Azhari, Hang Song, Shinsuke Sasada, Atsushi Iwata

IEEE Trans. Biomed. Circuits Syst., 2020

2019

Shifting Clock Jitter and Phase Interval for Impulse-Radar-Based Breast Cancer Detection.

Akihiro Toya, Takamaro Kikkawa, Yoshihiro Masui, Mitsutoshi Sugawara, Hiroyuki Ito, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Atsushi Iwata

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018

Gaussian Monocycle Pulse Generator with Calibration Circuit for Breast Cancer Detection.

Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa

Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017

Investigation of phase noise and jitter in CMOS sampling clock generation circuits for time-domain breast cancer detection system.

Akihiro Toya, Yoshihiro Masui, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Differential equivalent time sampling receiver for breast cancer detection.

Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2014

An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality.

Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi

Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2011

Wide-Dynamic-Range APS-Based Silicon Retina With Brightness Constancy.

Kazuhiro Shimonomura, Seiji Kameda, Atsushi Iwata, Tetsuya Yagi

IEEE Trans. Neural Networks, 2011

Background Calibration Techniques for Low-Power and High-Speed Data Conversion.

Atsushi Iwata, Yoshitaka Murasaka, Tomoaki Maeda, Takafumi Ohmoto

IEICE Trans. Electron., 2011

A New Multi-Path Routing Methodology Based on Logit-Type Probability Assignment.

Yudai Honma, Masaki Aida, Hideyuki Shimonishi, Atsushi Iwata

IEICE Trans. Commun., 2011

2010

A Neural Recording Amplifier with Low-Frequency Noise Suppression.

Takeshi Yoshida, Yoshihiro Masui, Ryoji Eki, Atsushi Iwata, Masayuki Yoshida, Kazumasa Uematsu

IEICE Trans. Electron., 2010

2009

A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion.

Yoshihiro Masui, Takeshi Yoshida, Atsushi Iwata

IEICE Trans. Electron., 2009

A 1.0-V 10-b 30-MS/s 3.4-mW rail-to-rail pipelined ADC using a new front-end MDAC.

Kunihiko Gotoh, Hiroshi Ando, Atsushi Iwata

IEICE Electron. Express, 2009

A Neural Signal Detection Amplifier with Low-frequency Noise Suppression.

Takeshi Yoshida, Yoshihiro Masui, Ryoji Eki, Atsushi Iwata, Masayuki Yoshida, Kazumasa Uematsu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Building Hierarchical Switch Network Using OpenFlow.

Hideyuki Shimonishi, Hideya Ochiai, Nobuyuki Enomoto, Atsushi Iwata

Proceedings of the 1st International Conference on Intelligent Networking and Collaborative Systems, 2009

2008

Low power and low voltage chopper amplifier without LPF.

Yoshihiro Masui, Takeshi Yoshida, Atsushi Iwata

IEICE Electron. Express, 2008

Off-the-path flow handling mechanism forhigh-speed and programmable traffic management.

Hideyuki Shimonishi, Takashi Yoshikawa, Atsushi Iwata

Proceedings of the ACM SIGCOMM 2008 Workshop on Programmable Routers for Extensible Services of Tomorrow, 2008

High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections.

Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata

Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008

High-Speed, Short-Latency Multipath Ethernet for Data Center Area Communications.

Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata

Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

2007

Crankback Signaling Extensions for MPLS and GMPLS RSVP-TE.

Adrian Farrel, Arun Satyanarayana, Atsushi Iwata, Norihito Fujita, Gerald R. Ash

RFC, July, 2007

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification.

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits.

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices.

Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki

IEICE Trans. Electron., 2007

Multilayer In-service Reconfiguration for Network Computing Systems.

Nobuharu Kami, Jun Suzuki, Yoichi Hidaka, Takashi Yoshikawa, Atsushi Iwata

Proceedings of the Sixth IEEE International Symposium on Network Computing and Applications (NCA 2007), 12, 2007

On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications.

Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique.

Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation.

Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

NAT Traversal Technology of Reducing Load on Relaying Server for P2P Connections.

Hideo Yoshimi, Nobuyuki Enomoto, Zhenlong Cui, Kazuo Takagi, Atsushi Iwata

Proceedings of the 4th IEEE Consumer Communications and Networking Conference, 2007

2006

A study of interference in synchronous systems.

Tsutomu Yoshimura, Atsushi Iwata

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique.

Takeshi Yoshida, Yoshihiro Masui, Takayuki Mashimo, Mamoru Sasaki, Atsushi Iwata

IEICE Trans. Electron., 2006

Improving Ethernet Reliability and Stability Using Global Open Ethernet Technology.

Masaki Umayabashi, Yoichi Hidaka, Nobuyuki Enomoto, Daisaku Ogasahara, Kazuo Takagi, Atsushi Iwata, Akira Arutaki

IEICE Trans. Commun., 2006

A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory.

Kan'ya Sasaki, Takashi Morie, Atsushi Iwata

IEICE Trans. Electron., 2006

An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture.

Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata

IEICE Trans. Electron., 2006

Carrier-Grade Ethernet Technologies for Next Generation Wide Area Ethernet.

Atsushi Iwata

IEICE Trans. Commun., 2006

20GHz uniform-phase uniform-amplitude standing-wave clock distribution.

Mitsuru Shiozaki, Mamoru Sasaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda

IEICE Electron. Express, 2006

FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation.

Teppei Nakano, Takashi Morie, Hideaki Ishizu, Hiroshi Ando, Atsushi Iwata

Intell. Autom. Soft Comput., 2006

ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform.

Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata

Proceedings of the 14th IEEE Symposium on High-Performance Interconnects, 2006

Proposal & demonstration of a new remote home-access system, softwire.

Hideo Yoshimi, Nobuyuki Enomoto, Chinryu Sai, Kazuo Takagi, Atsushi Iwata

Proceedings of the 3rd IEEE Consumer Communications and Networking Conference, 2006

Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated by Various Window Sizes.

Kan'ya Sasaki, Seiji Kameda, Atsushi Iwata

Proceedings of the Computer Vision, 2006

2005

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors.

Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata

J. Robotics Mechatronics, 2005

A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation.

Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata

J. Robotics Mechatronics, 2005

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique.

Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata

IEICE Trans. Electron., 2005

A 1V supply successive approximation ADC with rail-to-rail input voltage range.

Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations.

Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata

Proceedings of the Advances in Natural Computation, First International Conference, 2005

2004

Global open ethernet (GOE) system and its performance evaluation.

Atsushi Iwata, Yoichi Hidaka, Masaki Umayabashi, Nobuyuki Enomoto, Akira Arutaki

IEEE J. Sel. Areas Commun., 2004

A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture.

Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata

J. Intell. Fuzzy Syst., 2004

An analysis of interference in synchronous systems.

Tsutomu Yoshimura, Atsushi Iwata

IEICE Electron. Express, 2004

Gabor-Type Filtering using Transient States of Cellular Neural Networks.

Takashi Morie, Jun Umezawa, Atsushi Iwata

Intell. Autom. Soft Comput., 2004

Coarse-grain replica management strategies for dynamic replication of Web contents.

Norihito Fujita, Yuichi Ishikawa, Atsushi Iwata, Rauf Izmailov

Comput. Networks, 2004

A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition.

Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata

Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2004

Design of multiple reverse spanning trees in next generation of Ethernet-VPNs.

Aleksandar Kolarov, Bhaskar Sengupta, Atsushi Iwata

Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2003

A High-Resolution CMOS Image Sensor with Hadamard Transform Function.

Kousuke Katayama, Atsushi Iwata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture.

Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata

Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2003

A substrate noise analysis methodology for large-scale mixed-signal ICs.

Wen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002

Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques.

Hiroshi Ando, Takashi Morie, Makoto Miyake, Makoto Nagata, Atsushi Iwata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models.

Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Coarse-grain dynamic replication schemes for scalable content delivery networks.

Norihito Fujita, Nobuyuki Enomoto, Atsushi Iwata, Rauf Izmailov

Proceedings of the Global Telecommunications Conference, 2002

Modeling substrate noise generation in CMOS digital integrated circuits.

Makoto Nagata, Takashi Morie, Atsushi Iwata

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

A cellular-automaton-type image extraction algorithm and its implementation using an FPGA.

Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

Physical design guides for substrate noise reduction in CMOS digital circuits.

Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata

IEEE J. Solid State Circuits, 2001

A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution.

Shigeo Kinoshita, Takashi Morie, Makoto Nagata, Atsushi Iwata

IEEE J. Solid State Circuits, 2001

An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures.

Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata

Proceedings of the Advances in Neural Information Processing Systems 14 [Neural Information Processing Systems: Natural and Synthetic, 2001

Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation.

Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Adaptive and efficient multiple path pre-computation for QoS routing protocols.

Norihito Fujita, Atsushi Iwata

Proceedings of the Global Telecommunications Conference, 2001

Test circuits for substrate noise evaluation in CMOS digital ICs.

Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata

Proceedings of ASP-DAC 2001, 2001

2000

Measurements and analyses of substrate noise waveform inmixed-signal IC environment.

Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A hierarchical multilayer QoS routing system with dynamic SLA management.

Atsushi Iwata, Norihito Fujita

IEEE J. Sel. Areas Commun., 2000

ATM Routing Algorithms for Multimedia Traffic in Private ATM Networks.

Rauf Izmailov, Atsushi Iwata, Bhaskar Sengupta

J. Heuristics, 2000

Pulse modulation circuit architecture and its application to functional image sensors.

Atsushi Iwata, Makoto Nagata, Noriaki Takeda, Mitsuru Homma, Takashi Morie

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Quantitative characterization of substrate noise for physical design guides in digital circuits.

Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

A smart imager for the vision processing front-END.

Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata

Proceedings of ASP-DAC 2000, 2000

Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial.

Makoto Nagata, Atsushi Iwata

Proceedings of ASP-DAC 2000, 2000

An arbitrary chaos generator core curcuit using PWM/PPM signals.

Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata

Proceedings of ASP-DAC 2000, 2000

1999

Scalable routing strategies for ad hoc wireless networks.

Atsushi Iwata, Ching-Chuan Chiang, Guangyu Pei, Mario Gerla, Tsu-Wei Chen

IEEE J. Sel. Areas Commun., 1999

A Feature Associative Processor for Image Recognition Based on A-D merged Architecture.

Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie

Proceedings of the VLSI: Systems on a Chip, 1999

Measurements and analyses of substrate noise waveform in mixed signal IC environment.

Makoto Nagata, Yoji Kashima, Daisuke Tamura, Takashi Morie, Atsushi Iwata

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

A PWM signal processing core circuit based on a switched current integration technique.

Makoto Nagata, Jun Funakoshi, Atsushi Iwata

IEEE J. Solid State Circuits, 1998

Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation.

Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata

Proceedings of the Fifth International Conference on Neural Information Processing, 1998

Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method.

Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata

Proceedings of the Fifth International Conference on Neural Information Processing, 1998

QOS aggregation algorithms in hierarchical ATM networks.

Atsushi Iwata, Hiroshi Suzuki, Rauf Izmailov, Bhaskar Sengupta

Proceedings of the 1998 IEEE International Conference on Communications, 1998

1995

ATM Connection and Traffic Management Schemes for Multimedia Internetworking.

Atsushi Iwata, N. Mori, Chinatsu Ikeda, Hiroshi Suzuki, Maximilian Ott

Commun. ACM, 1995

1989

A 17 bit oversampling D-A conversion technology using multistage noise shaping.

Yasuyuki Matsuya, Kuniharu Uchimura, Atsushi Iwata, Takao Kaneko

IEEE J. Solid State Circuits, August, 1989

1988

Performance limits of mixed analog/digital circuits with scaled MOSFETs.

Eiichi Sano, Tsuneo Tsukahara, Atsushi Iwata

IEEE J. Solid State Circuits, August, 1988

Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators.

Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura, Atsushi Iwata

IEEE Trans. Acoust. Speech Signal Process., 1988

1986

A ring array processor architecture for highly parallel dynamic time warping.

Junichi Takahashi, Takashi Kimura, Sanshiro Hattori, Atsushi Iwata

IEEE Trans. Acoust. Speech Signal Process., 1986

VLSI- A to D and D to A converters with multi-stage noise shaping modulators.

Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura, Atsushi Iwata

Proceedings of the IEEE International Conference on Acoustics, 1986

A 50ns floating-point signal processor VLSI.

Takao Kaneko, Hironori Yamauchi, Atsushi Iwata

Proceedings of the IEEE International Conference on Acoustics, 1986

1985

An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM.

Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono

Proceedings of the IEEE International Conference on Acoustics, 1985

1982

A high quality ADM LSI codec at 32 kbit/s for digital speech communications.

Naohisa Ohta, Kazunari Irie, Takehiko Uno, Atsushi Iwata, Tomonori Aoyama

Proceedings of the IEEE International Conference on Acoustics, 1982