Atsushi Fujiwara

According to our database, Atsushi Fujiwara authored at least 9 papers between 1993 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

High-Density and Large-Scale MEA System Featuring 236, 880 Electrodes at 11.72μm Pitch for Neuronal Network Analysis.

Yuri Kato, Yoshihisa Matoba, Katsumi Honda, Koji Ogawa, Kan Shimizu, Masataka Maehara, Atsushi Fujiwara, Aoi Odawara, Chigusa Yamane, Naohiko Kimizuka, Jun Ogi, Tadayuki Taura, Ikuro Suzuki, Yusuke Oike

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2006

A simple and efficient hop-by-hop congestion control protocol for wireless mesh networks.

Bahareh Sadeghi, Akira Yamada, Atsushi Fujiwara, L. Lily Yang

Proceedings of the 2nd International ICST Conference on Wireless Internet, 2006

EDCA Based Congestion Control for WLAN Mesh Networks.

Akira Yamada, Atsushi Fujiwara, L. Lily Yang, Bahareh Sadeghi

Proceedings of the 63rd IEEE Vehicular Technology Conference, 2006

2005

Evaluation of Cell Coverage and System Throughput in Multihop DS-CDMA Cellular Network.

Atsushi Fujiwara, Shinji Takeda, Hitoshi Yoshino, Narumi Umeda

IEICE Trans. Commun., 2005

Centralized Channel Allocation Technique to Alleviate Exposed Terminal Problem in CSMA/CA-Based Mesh Networks - Solution Employing Chromatic Graph Approach - .

Atsushi Fujiwara, Yoichi Matsumoto

IEICE Trans. Commun., 2005

2002

A 63-μW standby power microcontroller with on-chip hybrid regulator scheme.

Mitsuru Hiraki, Takayasu Ito, Atsushi Fujiwara, Taichi Ohashi, Tetsuro Hamano, Takaaki Noda

IEEE J. Solid State Circuits, 2002

Multi-hop radio access cellular concept for fourth-generation mobile communications system.

Yasushi Yamao, Toru Otsu, Atsushi Fujiwara, Hidekazu Murata, Susumu Yoshida

Proceedings of the 13th IEEE International Symposium on Personal, 2002

1997

Non-linear PID controller using neural networks.

Toshiham Matsukuma, Atsushi Fujiwara, Munehiro Namba, Yoshihisa Ishida

Proceedings of International Conference on Neural Networks (ICNN'97), 1997

1993

A New Testing Acceleration Chip for Low-Cost Memory Tests.

Michihiro Inoue, Toshio Yamada, Atsushi Fujiwara

IEEE Des. Test Comput., 1993