Atsuo Watanabe

According to our database, Atsuo Watanabe authored at least 3 papers between 1989 and 1992.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1992

A 1.5-V full-swing BiCMOS logic circuit.

Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki

IEEE J. Solid State Circuits, November, 1992

1990

The SDC cell-A novel design methodology for high-speed arithmetic modules using CMOS/BiCMOS precharged circuits.

Takehisa Hayashi, Toshio Doi, Mitsuo Asai, Kenichi Ishibashi, Shoji Shukuri, Atsuo Watanabe, Makoto Suzuki

IEEE J. Solid State Circuits, April, 1990

1989

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM.

Makoto Suzuki, Suguru Tachibana, Atsuo Watanabe, Shoji Shukuri, Hisayuki Higuchi, Takahiro Nagano, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, October, 1989