Atishay

According to our database¹, Atishay authored at least 2 papers in 2019.

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2019

SEARS: A Statistical Error and Redundancy Analysis Simulator.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A Statistical Wafer Scale Error and Redundancy Analysis Simulator.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: New Technology Enabler, 2019