Atin Mukherjee

Int. J. Circuit Theory Appl., May, 2024

Design of a low-area hardware architecture to predict early signs of sudden cardiac arrests.

[BibT_eX]

[DOI]

Anusaka Gon

Microprocess. Microsystems, 2024

2023

High performance radiation-hardened SRAM cell design for robust applications.

[BibT_eX]

[DOI]

Microelectron. J., October, 2023

FPGA-Based Low-Cost Architecture for R-Peak Detection and Heart-Rate Calculation Using Lifting-Based Discrete Wavelet Transform.

[BibT_eX]

[DOI]

Anusaka Gon

Circuits Syst. Signal Process., 2023

Design of Single Node Upset Resilient Latch for Low Power, Low Cost and Highly Robust Applications.

[BibT_eX]

[DOI]

Anwesh Kumar Samal

Proceedings of the IEEE International Test Conference in Asia, 2023

2021

A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020

Defect Tolerant Approach for Reliable Majority Voter Design Using Quadded Transistor Logic.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Region 10 Conference, 2020

2019

Triple transistor based triple modular redundancy with embedded voter circuit.

[BibT_eX]

[DOI]

Microelectron. J., 2019

Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018

Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2018

2017

Triple transistor based fault tolerance for resource constrained applications.

[BibT_eX]

[DOI]

Microelectron. J., 2017

2016

Choice of granularity for reliable circuit design using dynamic reconfiguration.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

2015

Real-time fault-tolerance with hot-standby topology for conditional sum adder.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

New triple-transistor based defect-tolerant systems for reliable digital architectures.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2012

Design of a Fault-Tolerant Conditional Sum Adder.

[BibT_eX]

[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture.

[BibT_eX]

[DOI]