Athanasios Chatzidimitriou

Orcid: 0000-0001-8161-7165

According to our database1, Athanasios Chatzidimitriou authored at least 29 papers between 2015 and 2022.

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Bibliography

2022
On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study.
IEEE Trans. Sustain. Comput., 2022

The Impact of CPU Voltage Margins on Power-Constrained Execution.
IEEE Trans. Sustain. Comput., 2022

2021
A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs.
CoRR, 2021

2020
Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins.
CoRR, 2020

rACE: Reverse-Order Processor Reliability Analysis.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Anatomy of microarchitecture-level reliability assessment for modern processors
PhD thesis, 2019

SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.
IEEE Trans. Computers, 2019

Assessing the Effects of Low Voltage in Branch Prediction Units.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Multi-Bit Upsets Vulnerability Analysis of Modern Microprocessors.
Proceedings of the IEEE International Symposium on Workload Characterization, 2019

Adaptive Voltage/Frequency Scaling and Core Allocation for Balanced Energy and Performance on Multicore CPUs.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Demystifying Soft Error Assessment Strategies on ARM CPUs: Microarchitectural Fault Injection vs. Neutron Beam Experiments.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

2018
Statistical Analysis of Multicore CPUs Operation in Scaled Voltage Conditions.
IEEE Comput. Archit. Lett., 2018

Micro-Viruses for Fast System-Level Voltage Margins Characterization in Multicore CPUs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

HealthLog Monitor: A Flexible System-Monitoring Linux Service.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Analysis and Characterization of Ultra Low Power Branch Predictors.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs.
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018


2017
Performance-aware reliability assessment of heterogeneous chips.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Harnessing voltage margins for energy efficiency in multicore CPUs.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Voltage margins identification on commercial x86-64 multicore microprocessors.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2017

2016
Faults in data prefetchers: Performance degradation and variability.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Cross-layer system reliability assessment framework for hardware faults.
Proceedings of the 2016 IEEE International Test Conference, 2016

Anatomy of microarchitecture-level reliability assessment: Throughput and accuracy.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Differential Fault Injection on Microarchitectural Simulators.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

Accelerated microarchitectural Fault Injection-based reliability assessment.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015


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