Asuncion Perez-Pascual

Orcid: 0000-0002-6925-6878

According to our database1, Asuncion Perez-Pascual authored at least 22 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
O-City: Implementation of an Innovative Multimedia Platform for Promoting Orange Economy.
ACM Journal on Computing and Cultural Heritage, February, 2024

2018
Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders.
IEEE Access, 2018

2015
A 630 Mbps non-binary LDPC decoder for FPGA.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2012
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes.
J. Signal Process. Syst., 2012

Fully-parallel LUT-based (2048, 1723) LDPC code decoder for FPGA.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

High-throughput FPGA-based emulator for structured LDPC codes.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2009
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications.
J. Signal Process. Syst., 2009

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems.
J. Signal Process. Syst., 2009

FPGA-implementation of Time-Multiplexed Multiple Constant Multiplication based on carry-save arithmetic.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN.
J. Signal Process. Syst., 2008

2007
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs.
J. VLSI Signal Process., 2007

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices.
IEEE Trans. Educ., 2007

Design of an efficient digital down-converter for a SDR-based DVB-S receiver.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
The use of CORDIC in software defined radios: a tutorial.
IEEE Commun. Mag., 2006

Design of high performance timing recovery loops for communication applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2005
Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2003
DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002
FPGA-based radix-4 butterflies for HIPERLAN/2.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Distributed arithmetic radix-2 butterflies for FPGA.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

FPGA based on-line complex-number multipliers.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

1999
Efficient complex-number multipliers mapped on FPGA.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999


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