Astrit Ademaj

According to our database, Astrit Ademaj authored at least 18 papers between 2002 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

Self-configuration of IEEE 802.1 TSN networks.

Marina Gutiérrez, Astrit Ademaj, Wilfried Steiner, Radu Dobrin, Sasikumar Punnekkat

Proceedings of the 22nd IEEE International Conference on Emerging Technologies and Factory Automation, 2017

2011

Application-Level Diagnostic and Membership Protocols for Generic Time-Triggered Systems.

Marco Serafini, Péter Bokor, Neeraj Suri, Jonny Vinter, Astrit Ademaj, Wolfgang Brandstätter, Fulvio Tagliabo, Jens Koch

IEEE Trans. Dependable Secur. Comput., 2011

2008

Segmentation of standard ethernet messages in the time-triggered ethernet.

Vaclav Mikolasek, Astrit Ademaj, Stanislav Racek

Proceedings of 13th IEEE International Conference on Emerging Technologies and Factory Automation, 2008

2007

Experimental Evaluation of the DECOS Fault-Tolerant Communication Layer.

Jonny Vinter, Henrik Eriksson, Astrit Ademaj, Bernhard Leiner, Martin Schlager

Proceedings of the Computer Safety, 2007

Hardware Implementation of the Time-Triggered Ethernet Controller.

Klaus Steinhammer, Astrit Ademaj

Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

A Tunable Add-On Diagnostic Protocol for Time-Triggered Systems.

Marco Serafini, Neeraj Suri, Jonny Vinter, Astrit Ademaj, Wolfgang Brandstätter, Fulvio Tagliabo, Jens Koch

Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

2006

Combination of clock-state and clock-rate correction in fault-tolerant distributed systems.

Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik

Real Time Syst., 2006

A Composable Algorithm for Clock Synchronization in Multi-Cluster Real-Time Systems.

Alexander Hanzlik, Astrit Ademaj

Proceedings of the 4th International Workshop on Intelligent Solutions in Embedded Systems, 2006

A time-triggered ethernet (TTE) switch.

Klaus Steinhammer, Petr Grillinger, Astrit Ademaj, Hermann Kopetz

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Fault-Tolerant Time-Triggered Ethernet Configuration with Star Topology.

Astrit Ademaj, Hermann Kopetz, Petr Grillinger, Klaus Steinhammer, Alexander Hanzlik

Proceedings of the ARCS 2006, 2006

2005

The Time-Triggered Ethernet (TTE) Design.

Hermann Kopetz, Astrit Ademaj, Petr Grillinger, Klaus Steinhammer

Proceedings of the Eighth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2005), 2005

A Maintenance-Oriented Fault Model for the DECOS Integrated Diagnostic Architecture.

Philipp Peti, Roman Obermaisser, Astrit Ademaj, Hermann Kopetz

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004

Integration of Internal and External Clock Synchronization by the Combination of Clock-State and Clock-Rate Correction in Fault-Tolerant Distributed Systems.

Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik

Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004

2003

Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology.

Astrit Ademaj, Håkan Sivencrona, Günther Bauer, Jan Torin

Proceedings of the 2003 International Conference on Dependable Systems and Networks (DSN 2003), 2003

2002

Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods.

Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan Hlavicka

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Setting break-points in distributed time-triggered architecture.

Idriz Smaili, Astrit Ademaj

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Slightly-off-specification failures in the time-triggered architecture.

Astrit Ademaj

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

A Methodology for Dependability Evaluation of the Time-Triggered Architecture Using Software Implemented Fault Injection.

Astrit Ademaj

Proceedings of the Dependable Computing, 2002