Ashwini Sarathy
According to our database1,
Ashwini Sarathy
authored at least 7 papers
between 2007 and 2013.
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Bibliography
2013
Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
2009
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis.
IEEE Trans. Computers, 2008
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
2007
Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture.
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007