Ashwin Chintaluri

According to our database, Ashwin Chintaluri authored at least 4 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links.

Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Kaushik Narayanun, Shantanu Sarangi, Francisco Da Silva, Joe Sarmiento, Smbat Tonoyan, Ashwin Chintaluri, Animesh Khare, Milind Sonawane, Ashish Kumar, Anitha Kalva, Alex Hsu, Jayesh Pandey

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2016

Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays.

Ashwin Chintaluri, Helia Naeimi, Suriyaprakash Natarajan, Arijit Raychowdhury

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays.

Insik Yoon, Ashwin Chintaluri, Arijit Raychowdhury

Proceedings of the 2016 IEEE International Test Conference, 2016

2015

A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays.

Ashwin Chintaluri, Abhinav Parihar, Suriyaprakash Natarajan, Helia Naeimi, Arijit Raychowdhury

Proceedings of the 24th IEEE Asian Test Symposium, 2015