Ashutosh Pattnaik

Orcid: 0000-0003-0367-5989

According to our database1, Ashutosh Pattnaik authored at least 14 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Towards SLO-Compliant and Cost-Effective Serverless Computing on Emerging GPU Architectures.
Proceedings of the 25th International Middleware Conference, 2024

2021
Exploiting Activation based Gradient Output Sparsity to Accelerate Backpropagation in CNNs.
CoRR, 2021

ScaleDNN: Data Movement Aware DNN Training on Multi-GPU.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020
NEBULA: A Neuromorphic Spin-Based Ultra-Low Power Architecture for SNNs and ANNs.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
Distilling the Essence of Raw Video to Reduce Memory Usage and Energy at Edge Devices.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

CASH: compiler assisted hardware design for improving DRAM energy efficiency in CNN inference.
Proceedings of the International Symposium on Memory Systems, 2019

Opportunistic computing in GPU architectures.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
Quantifying Data Locality in Dynamic Parallelism in GPUs.
Proc. ACM Meas. Anal. Comput. Syst., 2018

2017
Controlled Kernel Launch for Dynamic Parallelism in GPUs.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Exploiting Core Criticality for Enhanced GPU Performance.
Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science, 2016

Measuring and modeling on-chip interconnect power on real hardware.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

μC-States: Fine-grained GPU Datapath Power Management.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Anatomy of GPU Memory System for Multi-Application Execution.
Proceedings of the 2015 International Symposium on Memory Systems, 2015


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