Ashutosh Chakraborty

According to our database, Ashutosh Chakraborty authored at least 22 papers between 2003 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

Skew Management of NBTI Impacted Gated Clock Trees.

Ashutosh Chakraborty, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Cell transformations and physical design techniques for 3D monolithic integrated circuits.

Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Giovanni De Micheli

ACM J. Emerg. Technol. Comput. Syst., 2013

2012

Reclaiming over-the-IP-block routing resources with buffering-aware rectilinear Steiner minimum tree construction.

Yilin Zhang, Ashutosh Chakraborty, Salim Chowdhury, David Z. Pan

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

Controlling NBTI degradation during static burn-in testing.

Ashutosh Chakraborty, David Z. Pan

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.

Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot, David Z. Pan, Giovanni De Micheli

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.

Ashutosh Chakraborty, Karthik Duraisami, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement.

Ashutosh Chakraborty, Sean X. Shi, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

PASAP: power aware structured ASIC placement.

Ashutosh Chakraborty, David Z. Pan

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.

Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Performance analysis of 3-D monolithic integrated circuits.

Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

On stress aware active area sizing, gate sizing, and repeater insertion.

Ashutosh Chakraborty, David Z. Pan

Proceedings of the 2009 International Symposium on Physical Design, 2009

Analysis and optimization of NBTI induced clock skew in gated clock trees.

Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan

Proceedings of the Design, Automation and Test in Europe, 2009

RegPlace: a high quality open-source placement framework for structured ASICs.

Ashutosh Chakraborty, Anurag Kumar, David Z. Pan

Proceedings of the 46th Design Automation Conference, 2009

2008

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.

Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino

IEEE Trans. Very Large Scale Integr. Syst., 2008

Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.

Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino

Integr., 2008

Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices.

Ashutosh Chakraborty, Sean X. Shi, David Z. Pan

Proceedings of the Design, Automation and Test in Europe, 2008

An integrated nonlinear placement framework with congestion and porosity aware buffer planning.

Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan

Proceedings of the 45th Design Automation Conference, 2008

2006

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.

Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.

Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Thermal resilient bounded-skew clock tree optimization methodology.

Ashutosh Chakraborty, Prassanna Sithambaram, Karthik Duraisami, Alberto Macii, Enrico Macii, Massimo Poncino

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.

Ashutosh Chakraborty, Enrico Macii, Massimo Poncino

Proceedings of the Integrated Circuit and System Design, 2005

2003

Low-Voltage, Double-Edge-Triggered Flip Flop.

Pradeep Varma, Ashutosh Chakraborty

Proceedings of the Integrated Circuit and System Design, 2003