Ashok Kumar Palaniswamy

According to our database, Ashok Kumar Palaniswamy authored at least 7 papers between 2008 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

ATPG for Delay Defects in Current Mode Threshold Logic Circuits.

Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2014

Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms.

Ashok Kumar Palaniswamy, Spyros Tragoudas

ACM J. Emerg. Technol. Comput. Syst., 2014

ATPG for transition faults of pipelined threshold logic circuits.

Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2012

An efficient heuristic to identify threshold logic functions.

Ashok Kumar Palaniswamy, Spyros Tragoudas

ACM J. Emerg. Technol. Comput. Syst., 2012

A scalable threshold logic synthesis method using ZBDDs.

Ashok Kumar Palaniswamy, Spyros Tragoudas

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2010

Scalable identification of threshold logic functions.

Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, Spyros Tragoudas

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2008

A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks.

Manoj Kumar Goparaju, Ashok Kumar Palaniswamy, Spyros Tragoudas

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008