Ashok Kumar

IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

Efficient Deep Learning Approach for Breast Cancer Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2024

Efficient Hardware Implementation of Artificial Neural Networks on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Low-Power Convolutional Neural Network Accelerator on FPGA.

[BibT_eX]

[DOI]

Kasem Khalil

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Reconfigurable Hardware Design Approach for Economic Neural Network.

[BibT_eX]

[DOI]

Kasem Khalil

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Adaptive Hardware Architecture for Neural-Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Cost-Efficient Reversible-Based Reconfigurable Ring Oscillator Physical Unclonable Function.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Economic Uniqueness-Improved Reliable Reconfigurable RO PUF for IoT Security.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Self-Healing Router Approach for High-Performance Network-on-Chip.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2021

A Cost-Efficient Reversible-Based Configurable Ring Oscillator Physical Unclonable Function.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

An Efficient Capsule Network Reconfigurable Hardware Accelerator for Deciphering Ancient Scripts with Scarce Annotations.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

A Hybrid Capsule Network-based Deep Learning Framework for Deciphering Ancient Scripts with Scarce Annotations: A Case Study on Phoenician Epigraphy.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

An In-Situ Sliding Window Approximate Inner-Product Scheme Based on Parallel Distributed Arithmetic for Ultra-Low Power Fault-Tolerant Applications.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

An Efficient Embryonic Hardware Architecture based on Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Reversible-Logic based Architecture for Convolutional Neural Network (CNN).

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Reversible-Logic Based Architecture for Long Short-Term Memory (LSTM) Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

An Efficient Reconfigurable Neural Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

A Reversible-Logic based Architecture for VGGNet.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

Machine Learning-Based Approach for Hardware Faults Prediction.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Intelligent Fault-Prediction Assisted Self-Healing for Embryonic Hardware.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2020

Dynamically Reconfigurable Deep Learning for Efficient Video Processing in Smart IoT Systems.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE World Forum on Internet of Things, 2020

Architecture of A Novel Low-Cost Hardware Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Reversible-Logic based Architecture for Artificial Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Novel Design Reversible Logic Based Configurable Fault-Tolerant Embryonic Hardware.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Economic LSTM Approach for Recurrent Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Self-healing hardware systems: A review.

[BibT_eX]

[DOI]

Microelectron. J., 2019

A Speed and Energy Focused Framework for Dynamic Hardware Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

N<sup>2</sup> OC: Neural-Network-on-Chip Architecture.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Novel Reconfigurable Hardware Architecture of Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Self-Healing Approach for Hardware Neural Network Architecture.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Novel Design Gate based Low-Cost Configurable RO PUF using Reversible Logic.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Demystifying Emerging Nonvolatile Memory Technologies: Understanding Advantages, Challenges, Trends, and Novel Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Unsupervised Ranking of Numerical Observations based on Magnetic Properties and Correlation Coefficient.

[BibT_eX]

[DOI]

Proceedings of the 52nd Hawaii International Conference on System Sciences, 2019

2018

Flexible Self-Healing Router for Reliable and High-Performance Network-an-Chips Architecture.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

An Efficient Approach for Neural Network Architecture.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Real-time streaming challenges in Internet of Video Things (IoVT).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2007

A network of sensor-based framework for automated visual surveillance.

[BibT_eX]

[DOI]

J. Netw. Comput. Appl., 2007

A framework for assessing residual energy in wireless sensor network.

[BibT_eX]

[DOI]

Mitun Bhattacharyya

Int. J. Sens. Networks, 2007

Design and Realization of Analog Phi-Function for LDPC Decoder.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Pixel-Level Image Fusion Scheme based on Linear Algebra.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Intelligent Mechanisms for Energy Reduction in Design of Wireless Sensor Networks using Learning Methods.

[BibT_eX]

[DOI]

Mitun Bhattacharyya

Proceedings of the Integrated Intelligent Systems for Engineering Design, 2006

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style.

[BibT_eX]

[DOI]

Sumeer Goel

IEEE Trans. Very Large Scale Integr. Syst., 2006

2005

Efficient shield insertion for inductive noise reduction in nanometer technologies.

[BibT_eX]

[DOI]

Mohamed A. Elgamel

IEEE Trans. Very Large Scale Integr. Syst., 2005

A Fast Scheduling Algorithm for Low Power Design.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2005

Autonomous Decentralized Systems Based Approach to Object Detection in Sensor Clusters.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2005

Low complexity decimation filter for multi-standard digital receivers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A systematic framework for high throughput MAP decoder VLSI architectures.

[BibT_eX]

[DOI]

Mahmoud Elassal

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An Architecture for Automated Scene Understanding.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005

2004

A methodology for low power scheduling with resources operating at multiple voltages.

[BibT_eX]

[DOI]

Mohamed A. Elgamel

Integr., 2004

1999

Minimizing switchings of the function units through binding for low power.

[BibT_eX]

[DOI]

Raghava V. Cherabuddi

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Multiple voltage-based scheduling methodology for low power in the high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Methodologies for binding function units for low power in high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Novel Formulations for Low-Power Binding of Function Units in High-Level Synthesis.

[BibT_eX]

[DOI]