Ashok K. Murugavel

According to our database, Ashok K. Murugavel authored at least 11 papers between 2001 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2004

Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis.

Ashok K. Murugavel, N. Ranganathan

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Gate Sizing and Buffer Insertion using Economic Models for Power Optimization.

Ashok K. Murugavel, N. Ranganathan

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

A game theoretic approach for power optimization during behavioral synthesis.

Ashok K. Murugavel, N. Ranganathan

IEEE Trans. Very Large Scale Integr. Syst., 2003

Petri net modeling of gate and interconnect delays for power estimation.

Ashok K. Murugavel, N. Ranganathan

IEEE Trans. Very Large Scale Integr. Syst., 2003

A Game-Theoretic Approach for Binding in Behavioral Synthesis.

Ashok K. Murugavel, N. Ranganathan

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization.

N. Ranganathan, Ashok K. Murugavel

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A low power scheduler using game theory.

N. Ranganathan, Ashok K. Murugavel

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002

Least-square estimation of average power in digital CMOS circuits.

Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali

IEEE Trans. Very Large Scale Integr. Syst., 2002

A Real Delay Switching Activity Simulator Based on Petri Net Modeling.

Ashok K. Murugavel, N. Ranganathan

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Power estimation of sequential circuits using hierarchical colored hardware petri net modeling.

Ashok K. Murugavel, N. Ranganathan

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001

Average Power in Digital CMOS Circuits using Least Square Estimation.

Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001