Ashkan Vakil

Orcid: 0000-0002-5029-8330

According to our database1, Ashkan Vakil authored at least 10 papers between 2019 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
RAPTA: A Hierarchical Representation Learning Solution For Real-Time Prediction of Path-Based Static Timing Analysis.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Golden-Chip Free Side Channel Delay Analysis Test for Hardware Trojan and Recycled IC Detection.
PhD thesis, 2021

AVATAR: NN-Assisted Variation Aware Timing Analysis and Reporting for Hardware Trojan Detection.
IEEE Access, 2021

Conditional Classification: A Solution for Computational Energy Reduction.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

A Reinforced Learning Solution for Clock Skew Engineering to Reduce Peak Current and IR Drop.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Learning Assisted Side Channel Delay Test for Detection of Recycled ICs.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Cluster-Based Partitioning of Convolutional Neural Networks, A Solution for Computational Energy and Complexity Reduction.
CoRR, 2020

ExTru: A Lightweight, Fast, and Secure Expirable Trust for the Internet of Things.
CoRR, 2020

LASCA: Learning Assisted Side Channel Delay Analysis for Hardware Trojan Detection.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019
IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019


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