Ashish Venkat

Orcid: 0000-0003-1959-8463

According to our database1, Ashish Venkat authored at least 24 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Abakus: Accelerating <i>k</i>-mer Counting with Storage Technology.
ACM Trans. Archit. Code Optim., March, 2024

Architectural Modeling and Benchmarking for Digital DRAM PIM.
Proceedings of the IEEE International Symposium on Workload Characterization, 2024

Special Session: Detecting and Defending Vulnerabilities in Heterogeneous and Monolithic Systems: Current Strategies and Future Directions.
Proceedings of the International Conference on Compilers, 2024

2023
Hardware Trojans in eNVM Neuromorphic Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Mitigating Speculative Execution Attacks via Context-Sensitive Fencing.
IEEE Des. Test, 2022

DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching.
IEEE Comput. Archit. Lett., 2022

SecSMT: Securing SMT Processors against Contention-Based Covert Channels.
Proceedings of the 31st USENIX Security Symposium, 2022

Speculative Code Compaction: Eliminating Dead Code via Speculative Microcode Transformations.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021
Agon: A Scalable Competitive Scheduler for Large Heterogeneous Systems.
CoRR, 2021

Sieve: Scalable In-situ DRAM-based Accelerator Designs for Massively Parallel k-mer Matching.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

I See Dead µops: Leaking Secrets via Intel/AMD Micro-Op Caches.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
Packet Chasing: Spying on Network Packets over a Cache Side-Channel.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

CHEx86: Context-Sensitive Enforcement of Memory Safety via Microcode-Enabled Capabilities.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management.
IEEE Micro, 2019

Platform-Agnostic Learning-Based Scheduling.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures.
Proceedings of the 10th International Workshop on Programming Models and Applications for Multicores and Manycores, 2019

Composite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISA.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Breaking the ISA Barrier in Modern Computing.
PhD thesis, 2018

Mobilizing the Micro-Ops: Exploiting Context Sensitive Decoding for Security and Energy Efficiency.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Reliability-Aware Data Placement for Heterogeneous Memory Architecture.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2016
HIPStR: Heterogeneous-ISA Program State Relocation.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2014
Harnessing ISA diversity: Design of a heterogeneous-ISA chip multiprocessor.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2012
Execution migration in a heterogeneous-ISA chip multiprocessor.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012


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