Ashish Srivastava
Orcid: 0000-0003-1439-1885
According to our database1,
Ashish Srivastava
authored at least 38 papers
between 2002 and 2024.
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Bibliography
2024
Optimizing routing in wireless sensor networks: leveraging pond skater and ant colony optimization algorithms.
Soft Comput., September, 2024
Enhancement in performance of cloud computing task scheduling using optimization strategies.
Clust. Comput., August, 2024
An efficacious neural network and DNA cryptography-based algorithm for preventing black hole attacks in MANET.
Soft Comput., March, 2024
Descriptive Analysis of OLSR Applicability to FANET with a Directional Antenna Based Various Propagation Models.
Wirel. Pers. Commun., February, 2024
CoRR, 2024
Proceedings of the Pattern Recognition - 27th International Conference, 2024
2023
Internet of Low-Altitude UAVs (IoLoUA): a methodical modeling on integration of Internet of "Things" with "UAV" possibilities and tests.
Artif. Intell. Rev., March, 2023
Wirel. Pers. Commun., 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
2022
Correction to: Edge Enhancement by Noise Suppression in HSI Color Model of UAV Video with Adaptive Thresholding.
Wirel. Pers. Commun., 2022
Edge Enhancement by Noise Suppression in HSI Color Model of UAV Video with Adaptive Thresholding.
Wirel. Pers. Commun., 2022
Int. J. Syst. Assur. Eng. Manag., 2022
Proceedings of the 2022 International Conference on Cyber Resilience (ICCR), 2022
2021
Machine learning approach for automatic diagnosis of Chlorosis in Vigna mungo leaves.
Multim. Tools Appl., 2021
VirLeafNet: Automatic analysis and viral disease diagnosis using deep-learning in <i>Vigna mungo</i> plant.
Ecol. Informatics, 2021
Future FANET with application and enabling techniques: Anatomization and sustainability issues.
Comput. Sci. Rev., 2021
CoRR, 2021
2020
Proceedings of the Intelligent Systems Design and Applications, 2020
2008
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
2007
Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proc. IEEE, 2007
2005
Series on Integrated Circuits and Systems, Springer, ISBN: 978-0-387-26528-5, 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.
Proceedings of the 42nd Design Automation Conference, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
A general framework for probabilistic low-power design space exploration considering process variation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Statistical optimization of leakage power considering process variations using dual-Vth and sizing.
Proceedings of the 41th Design Automation Conference, 2004
2003
An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
Statistical estimation of leakage current considering inter- and intra-die process variation.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002