Ashish Sharma

Affiliations:
  • Malaviya National Institute of Technology, Jaipur, India


According to our database1, Ashish Sharma authored at least 10 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
An improved reconfiguration algorithm for handling 1-point NoC failures.
Microprocess. Microsystems, 2023

2022
Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture.
Microprocess. Microsystems, June, 2022

2018
3D LBDR: Logic-Based Distributed Routing for 3D NoC.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2017
A Power, Thermal and Reliability-Aware Network-on-Chip.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016
<i>σ</i> <sup> <i>n</i> </sup>LBDR: generic congestion handling routing implementation for two-dimensional mesh network-on-chip.
IET Comput. Digit. Tech., 2016

Reducing FIFO buffer power using architectural alternatives at RTL.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015
A framework for thermal aware reliability estimation in 2D NoC.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Network-on-chip: Current issues and challenges.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Characterizing impacts of multi-Vt routers on power and reliability of Network-on-Chip.
Proceedings of the Eighth International Conference on Contemporary Computing, 2015

2014
Improved Route Selection Approaches using Q-learning framework for 2D NoCs.
Proceedings of the 3rd International Workshop on Many-core Embedded Systems (MES'2015) held on June 13, 2014


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