Ashish Sachdeva

Orcid: 0000-0003-2434-5073

According to our database1, Ashish Sachdeva authored at least 11 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2024
A Novel Simulation Approach for Fault Injection Mechanism Assessing Dependability of Cybersecurity Attacks.
J. Circuits Syst. Comput., April, 2024

Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications.
Circuits Syst. Signal Process., March, 2024

2023
Low Power Static Random-Access Memory Cell Design for Mobile Opportunistic Networks Sensor Nodes.
J. Circuits Syst. Comput., March, 2023

2022
Design of a soft error hardened SRAM cell with improved access time for embedded systems.
Microprocess. Microsystems, April, 2022

Characterization of Stable 12T SRAM with Improved Critical Charge.
J. Circuits Syst. Comput., 2022

2021
A Multi-bit Error Upset Immune 12T SRAM Cell for 5G Satellite Communications.
Wirel. Pers. Commun., 2021

Design of Low Power Half Select Free 10T Static Random-Access Memory Cell.
J. Circuits Syst. Comput., 2021

Design of 10T SRAM cell with improved read performance and expanded write margin.
IET Circuits Devices Syst., 2021

2020
Design of a Stable Low Power 11-T Static Random Access Memory Cell.
J. Circuits Syst. Comput., 2020

2018
The path to equilibrium in sequential and simultaneous games: A mousetracking study.
J. Econ. Theory, 2018

2012
Analog Textual Entailment and Spectral Clustering (ATESC) Based Summarization.
Proceedings of the Big Data Analytics, First International Conference, 2012


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