Ashish Ranjan

According to our database, Ashish Ranjan authored at least 17 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.

Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

Energy Efficient Cache Design with Piezoelectric FETs.

Reena Elangovan, Ashish Ranjan, Niharika Thakuria, Sumeet Kumar Gupta, Anand Raghunathan

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2021

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-Hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia M. Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

Approximate Memory Compression.

Ashish Ranjan, Arnab Raha, Vijay Raghunathan, Anand Raghunathan

IEEE Trans. Very Large Scale Integr. Syst., 2020

Emerging Neural Workloads and Their Impact on Hardware.

David Brooks, Martin M. Frank, Tayfun Gokmen, Udit Gupta, Xiaobo Sharon Hu, Shubham Jain, Ann Franchesca Laguna, Michael T. Niemier, Ian O'Connor, Anand Raghunathan, Ashish Ranjan, Dayane Reis, Jacob R. Stevens, Carole-Jean Wu, Xunzhao Yin

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Manna: An Accelerator for Memory-Augmented Neural Networks.

Jacob R. Stevens, Ashish Ranjan, Dipankar Das, Bharat Kaul, Anand Raghunathan

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks.

Ashish Ranjan, Shubham Jain, Jacob R. Stevens, Dipankar Das, Bharat Kaul, Anand Raghunathan

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Automatic Synthesis Techniques for Approximate Circuits.

Ashish Ranjan, Swagath Venkataramani, Shubham Jain, Younghoon Kim, Shankar Ganesh Ramasubramanian, Arnab Raha, Kaushik Roy, Anand Raghunathan

Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018

Computing in Memory With Spin-Transfer Torque Magnetic RAM.

Shubham Jain, Ashish Ranjan, Kaushik Roy, Anand Raghunathan

IEEE Trans. Very Large Scale Integr. Syst., 2018

AxBA: an approximate bus architecture framework.

Jacob R. Stevens, Ashish Ranjan, Anand Raghunathan

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

Approximate memory compression for energy-efficiency.

Ashish Ranjan, Arnab Raha, Vijay Raghunathan, Anand Raghunathan

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks.

Swagath Venkataramani, Ashish Ranjan, Subarno Banerjee, Dipankar Das, Sasikanth Avancha, Ashok Jagannathan, Ajaya Durg, Dheemanth Nagaraj, Bharat Kaul, Pradeep Dubey, Anand Raghunathan

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

STAxCache: An approximate, energy efficient STT-MRAM cache.

Ashish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2015

DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s.

Ashish Ranjan, Shankar Ganesh Ramasubramanian, Rangharajan Venkatesan, Vijay S. Pai, Kaushik Roy, Anand Raghunathan

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Approximate storage for energy efficient spintronic memories.

Ashish Ranjan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

AxNN: energy-efficient neuromorphic systems using approximate computing.

Swagath Venkataramani, Ashish Ranjan, Kaushik Roy, Anand Raghunathan

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

ASLAN: Synthesis of approximate sequential circuits.

Ashish Ranjan, Arnab Raha, Swagath Venkataramani, Kaushik Roy, Anand Raghunathan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014